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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chen, F. Shinosky, M. Li, B. Gambino, J. Mongeon, S. Pokrinchak, P. Aitken, J. Badami, D. Angyal, M. Achanta, R. Bonilla, G. Yang, G. Liu, P. Li, K. Sudijono, J. Tan, Y. Tang, T.J. Child, C. |
| Copyright Year | 2009 |
| Description | Author affiliation: Advanced Micro Devices, Inc, Hopewell Junction, NY 12533, USA (Child, C.) || IBM Microelectronics, Essex Junction, VT 05452, USA (Chen, F.; Shinosky, M.; Li, B.; Gambino, J.; Mongeon, S.; Pokrinchak, P.; Aitken, J.; Badami, D.) || IBM Microelectronics, Hopewell Junction, NY 12533, USA (Angyal, M.; Achanta, R.) || IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, USA (Bonilla, G.) || Chartered Semiconductor Manufacturing Ltd, Singapore 738406 (Yang, G.; Liu, P.; Li, K.; Sudijono, J.; Tan, Y.; Tang, T.J.) |
| Abstract | During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new “fatal” via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the “fatal” via ratio. |
| Starting Page | 464 |
| Ending Page | 475 |
| File Size | 695625 |
| Page Count | 12 |
| File Format | |
| ISBN | 9781424428885 |
| ISSN | 15417026 |
| DOI | 10.1109/IRPS.2009.5173298 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-26 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS technology Acceleration Noise robustness Leakage current Noise level Electric breakdown Stress Kinetic theory Voltage System testing I-V conduction slope time-dependent dielectric breakdown low-k soft breakdown Cu interconnect low-k hard breakdown reliability Schottky emission Poole-Frenkel low-k TDDB voltage acceleration low-k via TDDB |
| Content Type | Text |
| Resource Type | Article |
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