NDLI: BTI reliability of 45 nm high-K + metal-gate process technology

Content Provider	IEEE Xplore Digital Library
Author	Pae, S. Agostinelli, M. Brazier, M. Chau, R. Dewey, G. Ghani, T. Hattendorf, M. Hicks, J. Kavalieros, J. Kuhn, K. Kuhn, M. Maiz, J. Metz, M. Mistry, K. Prasad, C. Ramey, S. Roskowski, A. Sandford, J. Thomas, C. Thomas, J. Wiegand, C. Wiedemer, J.
Copyright Year	2008
Description	Author affiliation: PTD, Hillsboro, OR (Pae, S.)
Abstract	In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.
Starting Page	352
Ending Page	357
File Size	1543455
Page Count	6
File Format	PDF
ISBN	9781424420490
DOI	10.1109/RELPHY.2008.4558911
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High K dielectric materials High-K gate dielectrics MOS devices Gate leakage Hysteresis Leakage current Electron traps Thermal degradation Electrodes Logic Reliability BTI High-K Metal gate Transistors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dielectric breakdown in a 45 nm high-k/metal gate process technology

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

Reliability issues for high-k gate dielectrics

Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2 generation high-k/metal gate transistors

Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology

Characterization of leakage behaviors of high-k gate stacks by electron-beam-induced current

Process technology high-k i: metal gate stacks

Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

Process Technology - Gate Stack Process II - Metal Gate / High K Integration

BTI reliability of 45 nm high-K + metal-gate process technology

Similar Documents

Dielectric breakdown in a 45 nm high-k/metal gate process technology

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

Reliability issues for high-k gate dielectrics

Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2 generation high-k/metal gate transistors

Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology

Characterization of leakage behaviors of high-k gate stacks by electron-beam-induced current

Process technology high-k i: metal gate stacks

Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

Process Technology - Gate Stack Process II - Metal Gate / High K Integration

BTI reliability of 45 nm high-K + metal-gate process technology