NDLI: Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern

Content Provider	IEEE Xplore Digital Library
Author	Matsuyama, H. Suzuki, T. Ehara, H. Yanai, K. Kouno, T. Otsuka, S. Misawa, N. Nakamura, T. Mizushima, Y. Shiozu, M. Miyajima, M. Shono, K.
Copyright Year	2008
Description	Author affiliation: FUJITSU Ltd., Kuwana (Matsuyama, H.)
Abstract	Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types of voiding have a critical ldquowingrdquo area where failure never occurs. Both of voiding is more affected by diffusion source than by stress gradient.
Starting Page	683
Ending Page	684
File Size	155871
Page Count	2
File Format	PDF
ISBN	9781424420490
DOI	10.1109/RELPHY.2008.4558987
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Copper Stress Testing Immune system Life estimation Laboratories Ultra large scale integration Geometry Temperature Degradation extrusion pattern Stress migration Stress Induced Voiding Voiding inside VIA
Content Type	Text
Resource Type	Article

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Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern