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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jian Wang Li-Guang Chen Jin-Mei Lai |
| Copyright Year | 2006 |
| Description | Author affiliation: State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai (Jian Wang; Li-Guang Chen; Jin-Mei Lai) |
| Abstract | The most charming feature of FPGA is that it is post-fabricated, which means that user can design his own logic onto the chip without the need of tape out. So both design cycle and prototype cost can be greatly reduced. Once the bit file - which is a binary file representing the user designed logic generated, it should be downloaded into the chip to realize the user logic. This paper deals with the way of loading the bit file into the FPGA chip, which has been taped out with SMIC 0.18mum CMOS process this year. Daisy chain and CRC check circuits are designed in this FPGA chip. We use MODELSIM to verify the design before and after the layout is generated. The area of downloading circuit is less than 3 percent of the whole chip |
| Starting Page | 1950 |
| Ending Page | 1953 |
| File Size | 111054 |
| Page Count | 4 |
| File Format | |
| ISBN | 1424401607 |
| DOI | 10.1109/ICSICT.2006.306538 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-10-23 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Circuit synthesis Clocks Read-write memory Logic design Switches Cyclic redundancy check Logic circuits CMOS logic circuits Writing |
| Content Type | Text |
| Resource Type | Article |
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