NDLI: Achieving ultra low k dielectric constant for nanoelectronics interconnect systems

Content Provider	IEEE Xplore Digital Library
Author	Schulz, S.E. Schulze, K.
Copyright Year	2006
Description	Author affiliation: Center for Microtechnol., Chemnitz Univ. of Technol. (Schulz, S.E.; Schulze, K.)
Abstract	Air gaps are a promising alternative to porous low-k dielectrics to achieve ultra low k-values in Cu damascene interconnects. Two approaches of air gap formation using wet etch back of sacrificial PECVD $SiO_{2}$ dielectrics were evaluated concerning their feasibility and preparation results are shown. Electrical measurements were verified by simulation and have shown a capacitance reduction of approximately 50 % compared to the $SiO_{2}$ filled reference structures. Furthermore finite element method (FEM) simulations were performed to extract the effective k-value for different technology nodes. General k $_{eff}$ extraction procedure by FEM simulation is described. Furthermore the impact of variation of thickness and k-value of the functional layers applied for air gap formation was investigated. These functional layers are etch stop, cap and mask layers and currently consist of PECVD SiC:H films. It has been shown, that both parameters (thickness and k-value) considerably contribute to the effective k-value. For both investigated technology nodes, the 65 nm and 45 nm node, parameters can be found to fulfil the ITRS requirements for $k_{eff}.$ Lower k-values of the functional layers are needed, if the thickness has to be increased for processing reasons. For example k=5.5 and thickness of 15 nm yield a $k_{eff}$ of about 2.5 for the 45 nm node. Ultimate effective k-values of 2.0 and below could be achieved for lower k-value or thickness of the functional films
Starting Page	298
Ending Page	301
File Size	233655
Page Count	4
File Format	PDF
ISBN	1424401607
DOI	10.1109/ICSICT.2006.306212
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dielectric constant Nanoelectronics Wet etching Copper Chemical technology Air gaps Conducting materials Dielectric materials Integrated circuit interconnections Thermal conductivity
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Advanced interconnect schemes towards 0.1 /spl mu/m

Composite Dielectric/Metal Sidewall Barrier for Cu/Porous Ultra Low-k Damascene Interconnects

General review of issues and perspectives for advanced copper interconnections using air gap as ultra-low K material

Physical Failure Analysis techniques for Cu/low k technology

Advanced interconnect systems for ULSI technology

On-Chip Air-Gap Fabrication Using A New Sacrificial Polymer for Ultra Low-k Dielectrics

Copper interconnect technology for the 22 nm node

PEDL (polymer encapsulated dicing line) technology for copper/low-k dielectrics interconnect

Backside failure analysis and case studies for Cu/low k technology

Achieving ultra low k dielectric constant for nanoelectronics interconnect systems

Similar Documents

Advanced interconnect schemes towards 0.1 /spl mu/m

Composite Dielectric/Metal Sidewall Barrier for Cu/Porous Ultra Low-k Damascene Interconnects

General review of issues and perspectives for advanced copper interconnections using air gap as ultra-low K material

Physical Failure Analysis techniques for Cu/low k technology

Advanced interconnect systems for ULSI technology

On-Chip Air-Gap Fabrication Using A New Sacrificial Polymer for Ultra Low-k Dielectrics

Copper interconnect technology for the 22 nm node

PEDL (polymer encapsulated dicing line) technology for copper/low-k dielectrics interconnect

Backside failure analysis and case studies for Cu/low k technology

Achieving ultra low k dielectric constant for nanoelectronics interconnect systems