NDLI: Design of Switch Capacitor Integrator for DRSSADC

Content Provider	IEEE Xplore Digital Library
Author	Wangjian She Huang Lu Lizheng Dong
Copyright Year	2006
Description	Author affiliation: Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei (Wangjian She; Huang Lu; Lizheng Dong)
Abstract	Switch capacitor integrator circuits for dual-ramp-single-slop analog to digital converter (DRSSADC) is designed. The switch capacitor integrator uses a fully differential topology combined with input-to-output class AB amplifier and improved switch. Using the methods of Monte Carlo analysis and HSPICE simulation, the paper emphasizes to present design of the amplifier. Based on CSM 0.35mum CMOS process, the amplifier achieves high voltage gain and broad frequency band response under 3 V supply voltage, which consumes only 125 muW, achieving 74 dB open-loop gain, 8 MHz unity gain band width and 80deg phase margin for a load capacitance of 5 pF. And the integrator requires only 225 muW of power to meet the DRSSADC requirements
Starting Page	1769
Ending Page	1771
File Size	208467
Page Count	3
File Format	PDF
ISBN	1424401607
DOI	10.1109/ICSICT.2006.306421
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Voltage Switching circuits Switched capacitor circuits Analog-digital conversion Circuit topology Differential amplifiers Monte Carlo methods Analytical models Circuit simulation
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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