NDLI: A New Approach to Produce Cost-effective Known Good Die

Content Provider	IEEE Xplore Digital Library
Author	Kim, W. Lee, S.H. Hyun, I.H. Lee, K.J. Park, J.M.
Copyright Year	1994
Description	Author affiliation: Samsung Electronics, Korea (Kim, W.)
Abstract	Known good die is an enabling technology for the application on the wide range of electronic industry especially for multichip module application. Wafer level burn-in is an ideal methodology to produce KGD's, but there needs a considerable amount of time until it emerges to a viable process which should be practical and economical. In the mean time, die level burn-in becomes a common method to produce KGD for its practical application as several different types of burn-in carriers are commercially available. In this paper, a new cost effective process to produce KGD is proposed. Conventional wire bonding method was applied for electrical interconnection from chip to printed circuit board, designed for testing several chip together with a multichip holder. A proprietary tool was applied to cut gold wire from bond pad. Mass production of KGD was possible with the new process. Engineering samples, I Meg slow static RAM, produced by the new process showed excellent reliability and provided a significant amount of engineering data. It is believed that the new process can produce known good bare die most economically among existing die level burn-in methods. Because it used well established wire bonding technology rather than burn-in carrier to provide temporary contact between chip to test equipment which quite often proved unreliable in terms of contact resistance and can be used only limited number of times.
Starting Page	7
Ending Page	15
File Size	883332
Page Count	9
File Format	PDF
ISBN	0930815394
DOI	10.1109/ICMCM.1994.753522
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Wire Costs Bonding Printed circuits Mass production Electronics industry Gold Data engineering Reliability engineering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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