NDLI: On Wafer Burn-in Strategies for MCM Die

Content Provider	IEEE Xplore Digital Library
Author	Singh, A.D.
Copyright Year	1994
Description	Author affiliation: Auburn University, AL (Singh, A.D.)
Abstract	The high cost associated with replacing faulty die in many MCM technologies suggests that die used in their manufacture be known to be good with high confidence. This requires some burn-in of the die since significant "infant mortality" failures are observed for semiconductor parts. Burn-in generally involves mounting the die on temporary die carriers so that signals can be applied to activate the circuits. In this paper we present a more efficient strategy that allows the burn-in of the die on the wafer before they are diced. Our proposed approach requires that power, ground and clock connections to each die be fabricated on the wafer so that all the circuits can be powered up and clocked using only a few probe connects to the wafer. These extra connections use the space between die, and are lost once the wafer is diced into individual circuits. During burn-in, the circuits are activated in the built-in self test (BIST) mode. Here inputs to subcircuits within each die is provided by linear feedback shift registers. Power dissipation and thermal stress during burn-in is managed by controlling the air flow over the wafer surface and by appropriate selection of the thermal conduction properties of the temporary wafer carrier system employed. It is also possible to selectively power up subsets of the die to manage power dissipation. Wafer level burn-in promises to be a cost effective approach for delivering known good die.
Starting Page	255
Ending Page	260
File Size	418505
Page Count	6
File Format	PDF
ISBN	0930815394
DOI	10.1109/ICMCM.1994.753559
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Thermal stresses Costs Packaging Manufacturing Contacts Built-in self-test Thermal management Circuit faults Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in