NDLI: A Large Area, 3-D Stackable, Mcm-D on C Signal Processor

Content Provider	IEEE Xplore Digital Library
Author	Arndt, L.E.
Copyright Year	1994
Description	Author affiliation: Raytheon, Missile Systems Division, MA (Arndt, L.E.)
Abstract	Military applications for MCMs often require non-standard form factors tailored to fit the unique configurations of military systems. Size and weight requirements may further restrict the use of standard packaging and interconnect methods such as the typical SMT packages mounted on PWBs and backplanes. Cost and design cycle time considerations however argue in favor of standard configurations which can be used in multiple applications without incurring significant NRE costs or risks for each new application. An MCM approach will be presented which uses polymer thin film HDI deposited onto an LTCC substrate to provide a flexible form factor and a very high functional density, while maintaining the advantages of a standard, proven architecture and a fixed HDI layout. The HDI provides all internal chip-to-chip interconnect, while the LTCC acts as the package floor, redistributes primary I/O, and provides physical conformance to each target system. Hermetic sealing of the chips and HDI is accomplished by routinely brazing a Kovar seal ring onto the LTCC and subsequently seam welding a Kovar lid into place. This configuration also provides an I/O pad array interface which tends itself well to direct 3-D stacking of multiple MCMs in a "building block" fashion using only connectors but no PWB or backplane. MCMs have been successfully fabricated at two different HDI foundries, using Alumina substrates, while LTCC / HDI materials and processing techniques were matured. Testing of these MCMs has been successful with demonstrated performance superior to the PWB version of the circuit.
Starting Page	603
Ending Page	611
File Size	1316822
Page Count	9
File Format	PDF
ISBN	0930815394
DOI	10.1109/ICMCM.1994.753615
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing Packaging Backplanes Integrated circuit interconnections Costs Very large scale integration Missiles Polymers Substrates Stacking
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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