NDLI: Processing and reliability of flip-chip on board connections

Content Provider	IEEE Xplore Digital Library
Author	Collier, P.A. Teo, K.H.
Copyright Year	1997
Description	Author affiliation: Inst. of Microelectron., Singapore (Collier, P.A.)
Abstract	Processes with potential for low cost flip-chip on board assembly were investigated in order to populate conventional printed circuit cards directly or to replace wire bonding in ball grid array packages. Overall aspects of wafer bumping, device placement, underfill encapsulation and assembly integrity were addressed. Two types of wafer bumping process were evaluated, involving fine pitch stencil printing of solder pastes directly on wafers and the application of a wire bonding technique to deposit solder ball bumps on connection pads. To determine flip-chip on board process robustness and reliability, test vehicles were designed to accommodate a range of flip-chip dice, of sizes between 3.8 mm and 12.7 mm and with I/O between 21 and 1056. These vehicles allowed monitoring of electrical continuity through bumps connected in series in daisy chains, as well as including power dissipation and temperature sensing devices for thermal measurements and power cycling tests. The results of the evaluations are discussed, covering assessment of bumping process performance in terms of uniformity and pitch capability and the integrity of flip-chip assemblies determined by nondestructive analysis, mechanical testing and thermal shock testing.
Starting Page	251
Ending Page	258
File Size	1237722
Page Count	8
File Format	PDF
ISBN	0780341570
DOI	10.1109/EPTC.1997.723918
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Assembly Wire Wafer bonding Vehicles Nondestructive testing Costs Printed circuits Electronics packaging Encapsulation Printing
Content Type	Text
Resource Type	Article

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Board-level reliability of coreless flip chip package assembled on a printed circuit board

Comparison of the thermal performance of wire bonded and flip chip CSP's

Chip scale package implementation challenges

Low-cost, wafer level underfilling and reliability testing of flip chip devices

Flip chip on board (FCOB) process characterization

Wafer level encapsulation for system in package generation

Reliability of flip chip BGA package on organic substrate

High performance ball grid array utilizing flip chip bonding on buildup printed circuit board

Cost analysis: solder bumped flip chip versus wire bonding

Processing and reliability of flip-chip on board connections

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