NDLI: Global Optimization of MCMs with ASICs Using Concurrent Engineering

Content Provider	IEEE Xplore Digital Library
Author	Cazenave, J.-P. Dupenloup, G.
Copyright Year	1994
Description	Author affiliation: Dassault Electronique, France (Cazenave, J.-P.)
Abstract	This paper describes a large MCM developed for space applications. Design constraints were extremely severe: low volume, low weight, high signal speed, minimum power consumption, high pressure, exposition to space vacuum. The MCM includes 1.2 million of transistors. It required the design of 8 different types of ASICs in 3 different technologies: CMOS, ECL, mixed-signal bipolar. The substrate has been fabricated using Dassault Electronique's high-density photo-imageable thick-film process (PCM technology), that is briefly described in this paper. An Aluminium package was used to save weight and improve thermal conduction. Stand-offs sustaining the lid were used to handle high pressure. The MCM and the ASICs were concurrently designed to simplify the layout of the MCM as much as possible. Despite high routing density, only 4 layers were used. Heavy traffic was "pushed" into ASICs where there is no significant extra cost associated with connections. The ASIC pads were arranged to match MCM wires. A global Design-For-Test strategy has been implemented. The ASICs include internal and external Built-In Self Test (BIST) resources, that allow to test the ASICs and the MCM connections at full speed and with no external test vectors. Test modes can be controlled and defaults can be located through a single test bus based on the IEEE 1149.1 (JTAG) standard. The MCM can be fully tested with no other test equipment than a standard PC connected to its test bus.
Starting Page	396
Ending Page	401
File Size	507522
Page Count	6
File Format	PDF
ISBN	0930815394
DOI	10.1109/ICMCM.1994.753581
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Concurrent engineering Signal design Space technology Testing Packaging machines Energy consumption Aluminum CMOS technology Design for testability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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