NDLI: Implementing a Tab Tape-based Known Good Die Method

Content Provider	IEEE Xplore Digital Library
Author	Salatino, M. Nolan, R. Bishop, T. Bieber, C.
Copyright Year	1994
Description	Author affiliation: Microelectronics and Computer Technology Corporation (MCC) Austin, TX (Salatino, M.)
Abstract	The success of nearly every multichip electronic system depends on the availability of functional, reliable chips. As chip counts in a multichip system increase, this dependency is critical. In most cases, "known good" die (KGD) are not readily available in an unpackaged form. This was a prime consideration in MCC's. Flip Chip Development Project. As part of this project, MCC was chartered with developing a method for high speed test and dynamic burn-in of single, bare IC chips. The method developed can be implemented by bare die users using "off-the-shelf" technology. It can also be implemented by bare chip suppliers without modification to the existing fabrication processes. The heart of this process is a TAB tape-based carrier. TAB tape is used to contact the chip bond pads (without actual metallurgical bonding) at about 10 grams per lead contact force. The chip is clamped to the TAB leads, and held in place so that the tape site (in its JEDEC-standard slide carrier) can be transported, tested, and burned-in just like TAB chip-on-tape. Upon test completion, the chip is removed, and is ready for wire bonding, flip chip attach, etc. The carrier has been characterized with aluminum, gold, and solder-bumped chip bond pads, and is compatible with these pad metallizations. Four re-uses of the carrier through 168 hours/150"C of burn-in have been demonstrated. In this paper, the results of MCC's initial prototype testing are discussed. Data includes contact resistance vs. pressure, chip metallurgy, and time. The cost of this approach is presented for a wide range of production volumes. In addition, preliminary results from beta-site testing (by a bare chip supplier) of this method are presented.
Starting Page	16
Ending Page	22
File Size	692491
Page Count	7
File Format	PDF
ISBN	0930815394
DOI	10.1109/ICMCM.1994.753523
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Costs Flip chip Production Bonding forces Lead Packaging Microelectronics Aircraft Aerospace electronics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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