NDLI: Mcm Burn-In Experience

Content Provider	IEEE Xplore Digital Library
Author	Bardsley, T. Lisowski, J. Wilson, S. VanAernam, S.
Copyright Year	1994
Description	Author affiliation: IBM Microelectronics (Bardsley, T.)
Abstract	Multi-chip module burn-in has been utilized at IBM for several years. The current module burn-in tool stresses 121 chip multi-chip modules used in the IBM ES/9000 mainframes. MCM level burn-in has been performed on alumina and glass-ceramic substrates with bipolar and CMOS chip technologies resulting in various challenges to tool design and proem development. This paper will focus on the module burn-in tool, key technical challenges to implementing MCM burn-in and the experience of performing MCM level burn-in. The key technical challenges: thermal management, thermal/mechanical stress issues, electrical stimulation and module testability will be reviewed. The impact of design for test on burn-in will be discussed. A review of the defect mechanisms and experimental results will be covered. An overview of a cost model which compares MCM level burn-in against known-good-die burn-in will be reviewed to demonstrate the merits of module level burn-in. The paper will conclude with the future plans to address the rapidly expanding OEM MCM market.
Starting Page	223
Ending Page	229
File Size	560649
Page Count	7
File Format	PDF
ISBN	0930815394
DOI	10.1109/ICMCM.1994.753555
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing CMOS technology Substrates Thermal management Thermal stresses Packaging Microelectronics CMOS process Electrical stimulation Computer aided manufacturing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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