NDLI: A Cost-Effective Wafer-Level Burn-In Technology

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Proceedings 1997 International Conference on Multichip Modules

Proceedings of the International Conference on Multichip Modules

Proceedings of the 1994 International Conference on Multichip Modules

List of authors

The Promise of Known-good-die Technologies

A New Approach to Produce Cost-effective Known Good Die

Implementing a Tab Tape-based Known Good Die Method

Development of a Burn-in and Test Process for Producing Known-Good-Die

Comparison of Two Temporary Carriers for Test and Burn-In of Memory Die

A Cost-Effective Wafer-Level Burn-In Technology

Flip Chip Technology: A Method for Providing Known Good Die with High Density Interconnections

Fine Pitch Wedge Bonding for High Density Packaging

Thermoplastic Die Attach for Hermetic Packaging

Rework of Wire Bonded Devices on Mcms

Implementation of Advanced Micro-Interconnection Technologies on a Thin-Film Multichip Module

Cost Implications of Large Area MCM Processing

From Display and Pwb to Mcms: Large Panel Manufacturing

Large Format Fabrication a Practical Approach to Low Cost MCM-D

Large Format Mcm-D Processing Adaptation of the Hughes Hdmi/sup TM/ Process to Large Format Mcm-D: Options, Problems, Results to Date

Large Area Fine Line Patterning by Scanning Projection Lithography

Thin Film Transfer Process for Low Cost Mcm-D Fabrication

Cu/Photosensitive-BCB Thin-Film Multilayer Technology for High-Performance Multichip Module

An ATM Switching Module using MCM-C Technology

Stress Induced in Ceramics-Conductor of Mcm

Multichip module technologies for high-speed ATM switching systems

Mcm Substrate with High Capacitance

Heat-Pipe Cooling Technology for High-Speed Atm Switching Mcms

Mixed-Signal Mcm-L Design Using a Global Positioning System (gps) Receiver as an Example

The TCC/MCM: /spl mu/BGA on a laminated substrate

An Application Strategy for Scm-L and Mcm-L Using High Density Laminate Technologies

Mechanical Punching of Through-Holes in Thin Laminates for Higher Density MCM-L Fabrication

A Process for the Manufacture of Cost Competitive MCM Substrates

Interconnected Mesh Power System, (IMPS) A Packaging and Interconnection Application

Design and Test of a Complex Mcm Product

Algorithmic Diagnosis of Multichip Module Defects Using the IEEE 1149.1 Standard

Applications of Latent Open Test

Testing Multichip Modules and Bare Die Using Vision Probing Techniques

Boundary Scan Techniques in an Mcm-D Application

Mcm Burn-In Experience

Defect Migration of Multi-chip Modules Using Structural Test

High Performance Elastic Connection for Reliable Device Testing

Universal Membrane Probe for Known Good Die

On Wafer Burn-in Strategies for MCM Die

Known Good Die Selection Tradeoffs: A Cost Model

AT&T spl mu/Surface Mount Assembly: A New Technology for the Large Volume Fabrication of Cost Effective Flip-Chip MCMs

Advanced Mcm-d With Embedded Resistors

Development and Realization of a Doubleface Populated Multichip Module in Thin Film Technology for High Frequency Application

3-D Stacking Using the GE High Density Multichip Module Technology

Thin Film Programmable Interconnect Arrays

Interconnection Considerations for a Hybrid Mcm

Redefining the Economics of Mcm Applications

A High-Performance Second-Generation Sparc Mcm

Volume Implementation of MCM-D Based Cache SRAM Products for Workstation and PC Applications

MCM-L Technology: A Systems Cost Analysis for a High Volume Automotive Electronics Application

MCM-L Cost Model & Application Case Study

Evaluation of Non-Hermetic Coatings for Mcm Applications through Hast, 85/85 and Pct

An In-Situ Measurement Technique for Through-Plane Thermal Properties of Thin Dielectric Films

Stress Development During High Dielectric Ceramic Thin Films Processing

Fabrication, Assembly, and Characterization of Stacked Multichip Modules Using Hot Pressed, Co-Fired Aluminum Nitride

Evaluation of Ionic Salt Photodefinable Polyimides As Mcm-D Dielectrics with Copper Metallization

A Large Format Modified TEA CO/sub 2/ Laser Based Process for Cost Effective Small Via Generation

Development of a Dsp Function Using a Mcm Technology

An Mcm-D Foundry from Copper/polyimid Tfml Bare Substrate to Multichif Modules

Electroless Nickel/Copper Plating as a New Bump Metallization

Global Optimization of MCMs with ASICs Using Concurrent Engineering

Mcm-D Technology for a Communication Application

Advanced Mcm-L in Apachip a European Cooperative Program

Mcm-L Technologies: Myths and Experiences in Multiple Product Scenarios

Wire Bonding Dual-Sided Mcma Modules

Integrated Flex: Rigid-Flex Capability in a High Performance Mcm

Environmental Performance of Sealed Chip-On-Board (scob) Memory Circuits

Mcm-L Product Development Process for Low-Cost Mcms

Chip on Board Technology for Low Cost Multi-Chip-Modules

Thin-Profile MCM-D Packaging for Small Form Factor Applications

Non-Digital Extensions of an Embedded Chip MCM Technology

3-D Multichip Packaging for Memory Modules

Electrical Design of an Mcm for a Multiprocessor System

Capacitively Coupled Multichip Modules

Mcm-D Prototype of the Supersparc Chipset in Two Weeks

Array Module Connector Test Program at Unisys

Cost effective ceramic surface mount packaging for high I/O applications

Ball Grid Array Ceramic Packages

Effects of Ceramic Ball-Grid-Array Package's Manufacturing Variations on Solder Joint Reliability

Construction of Mother Boards Interconnecting Mcm's

Reliability Comparison of Two Metallurgies for Ceramic Ball Grid Array

The Essential Role of Custom Design Kits for Cost-Effective Access to the Mcm Foundry

Design of the Interconnected Mesh Power System (IMPS) MCM Topology

Choosing an Mcm Technology for Thermal Performance

Accurate I/O Models for High Speed Digital Design Using Spice Controlled Sources

CD3D: A Constraint-driven 3-dimensional Router for Thick Film Mcms

Solving Real World MCM Design Problems

A Four Asic Mcm-c, the "Kiss" Principle, and the Next Generation Silicon

A Twenty-Seven Chip MCM-C

A 50mhz Multichip Processor Module With Flip Chip Technology

Integrated Brazed Ltcc Packages

Dual-use Microelectronics Manufacturing Specification for Single and Multichip Packaging Technologies

A Large Area, 3-D Stackable, Mcm-D on C Signal Processor

Ltcc Mcm Technology for Military Environments

Active Silicon Substrate Multi-Chip Module Technology for Sensor Signal Processing and Control

Demonstration of a High Heat Removal Cvd Diamond Substrate Edge-Cooled Multichip Module

A Cost-Effective Wafer-Level Burn-In Technology

Content Provider	IEEE Xplore Digital Library
Author	Tuckerman, D.B. Jarvis, B. Chang-Ming Lin Patel, P. Hunt, M.
Copyright Year	1994
Description	Author affiliation: nCHIP, Inc., CA (Tuckerman, D.B.)
Abstract	A new wafer-level bum-in method is presented. The method incorporates a silicon "bum-in substrate" fabricated using MCM-D substrate technology, and includes integral isolation resistors. The novel, Si wafer-to Si wafer pressure contact technology is based on deformable solder bumps and is functional in a high temperature burn-in environment, immune to thermal expansion mismatch problems, reusable, and does not damage or contaminate bond pads. The method is suitable for high-volume production and can reduce bum-in costs, even for chips that are ultimately destined for single-chip packages.
Starting Page	34
Ending Page	40
File Size	702053
Page Count	7
File Format	PDF
ISBN	0930815394
DOI	10.1109/ICMCM.1994.753526
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Temperature Costs Isolation technology Thermal expansion Resistors Wafer bonding Probes Manufacturing Fixtures
Content Type	Text
Resource Type	Article

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