NDLI: An Application Strategy for Scm-L and Mcm-L Using High Density Laminate Technologies

Content Provider	IEEE Xplore Digital Library
Author	Houston, T. Heck, H. Knight, J.
Copyright Year	1994
Description	Author affiliation: IBM Microelectronics, NY (Houston, T.)
Abstract	As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.
Starting Page	167
Ending Page	172
File Size	318636
Page Count	6
File Format	PDF
ISBN	0930815394
DOI	10.1109/ICMCM.1994.753546
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Laminates Electronics packaging Wiring Flip chip Microelectronics Electronics industry Costs Material properties Electronic packaging thermal management Space technology
Content Type	Text
Resource Type	Article

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