NDLI: Pulsed power switching of 4H-SiC vertical D-MOSFET and device characterization

Content Provider	IEEE Xplore Digital Library
Author	Bilbao, A. Ray, W.B. Schrock, J.A. Bayne, S.B. Lin Cheng Agarwal, A.K. Scozzie, C.
Copyright Year	2013
Description	Author affiliation: Cree, Inc., Durham, NC, USA (Lin Cheng; Agarwal, A.K.) \|\| U.S. Army Res. Lab., Adelphi, MD, USA (Scozzie, C.) \|\| Electr. & Comput. Eng. Dept., Texas Tech Univ., Lubbock, TX, USA (Bilbao, A.; Ray, W.B.; Schrock, J.A.; Bayne, S.B.)
Abstract	Summary form only given. This research is to characterize and compare CREE's new N-Channel Silicon Carbide (4H-SiC) vertical power D-MOSFET with CREE's previous generation of N-Channel Silicon Carbide (4H-SiC) vertical power D-MOSFET. The new generation of D-MOSFET is rated for 1200V and 150A continuous; the previous generation D-MOSFET is rated for 1200V and 80A continuous. The active conducting area (0.4 $cm^{2})$ and chip size (0.56 $cm^{2})$ are identical in the two generations. The devices were tested on a RLC ring down low inductance test bed. Both generation 4H-SiC D-MOSFETs were tested at a gate to source voltage of 20V with 1200V drain to source using multiple gate resistances. Single and repetitive pulse switching was utilized for testing the devices. The testing utilized a pulse repetition rate up to 2000 pulses at 1 Hz. Throughout the testing, the devices were removed from the RLC ring down test bed and characterized on an Agilent B1505A curve tracer. Results gathered include: characteristic curves, transient pulse characteristics, stress failure points, device degradation, and device performance. The transient responses of the 150A device were analyzed using different gate resistances for the purpose of switching performance optimization. Testing determined that the new generation device was able to withstand a peak current pulse of 1100A, at a dI/dt of 516 A/μsec, and a peak current density of 2750 $A/cm^{2}$ without saturating. The previous generation was able to withstand a peak current pulse of 270A without saturating. The increased current handling capability is due to a 17% decreased on-state $R_{DS}$ at forward voltage drop of 1.2 V and gate bias of 20 V. These factors lead to a 400% increase in pulsed current handling capability over the previous generation device with the same active area.
Starting Page	1
Ending Page	1
File Size	110772
Page Count	1
File Format	PDF
ISBN	9781467351713
ISSN	07309244
DOI	10.1109/PLASMA.2013.6635035
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Testing Silicon carbide MOSFET Switches Transient analysis Switching circuits
Content Type	Text
Resource Type	Article
Subject	Atomic and Molecular Physics, and Optics Condensed Matter Physics Electrical and Electronic Engineering

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