NDLI: A single chip multi-functional DDS waveform generator based on FPGA with SOPC design flow

Content Provider	IEEE Xplore Digital Library
Author	Ruan Yue Tang Ying Yao Wen-ji Wang Zhang-quan Xu Sen
Copyright Year	2012
Description	Author affiliation: Zhejiang Shuren University, Hangzhou, China (Ruan Yue; Tang Ying; Yao Wen-ji; Wang Zhang-quan; Xu Sen)
Abstract	This work presents a highly integrated single chip multi-functional, multi-waveform signal generator which can generate various waveforms, with digital controller inside to adapt embedded and low power applications. The proposed system is composed by Nios II, DDS (Direct Digital Synthesis) and other peripherals. Nios II is a reconfigurable, programmable and optimizable soft-core embedded CPU. DDS is used to generate required waveforms. Together with modern EDA tools, the system HW/SW co-design and FPGA implementation is accomplished, using typical SOPC design flow. Utilizing characteristics of Nios II, the core and peripheral logical units that system need are put together and implanted into a single FPGA chip. The Avalon bus is used to connect peripheral modules (such as function switch buttons and 7-segment LED display units) to Nios II's Avalon bus main port (instruction and data control port). The realized system is flexible to reduce, extend, with low power consumption, and has System on Programmable Chip (SOPC) function which means the system's software and hardware is online programmable.
Starting Page	4206
Ending Page	4210
File Size	163674
Page Count	5
File Format	PDF
ISBN	9781467313971
e-ISBN	9781467313988
DOI	10.1109/WCICA.2012.6359183
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-06
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Hardware IP networks Signal generators Software Digital signal processing FPGA SOPC Nios II DDS signal generator
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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