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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Okoro, C. Levine, L.E. Ruqing Xu Obeng, Y.S. |
| Copyright Year | 2015 |
| Description | Author affiliation: Adv. Photon Source, Argonne Nat. Lab., Argonne, IL, USA (Ruqing Xu) || Semicond. & Dimensional Metrol. Div., Nat. Inst. of Stand. & Technol. (NIST), Gaithersburg, MD, USA (Okoro, C.; Obeng, Y.S.) || Mater. Sci. & Eng. Div., Nat. Inst. of Stand. & Technol. (NIST), Gaithersburg, MD, USA (Levine, L.E.) |
| Abstract | In this work, an experimental study of the influence of Cu through-silicon via (TSV) diameter on stress build up was performed using synchrotron-based X-ray microdiffraction technique. Three Cu TSV diameters were studied; 3 μm, 5 μm and 8 μm, all of which were fabricated in a single chip. Prior to the measurements, the die was annealed at 420 °C (30 min), yielding a fully grown and stable microstructure. The measured mean hydrostatic stresses in the Cu TSV were 185±14 MPa (3 μm Cu TSV diameter), 147±10 MPa (5 μm Cu TSV diameter) and 205±15 MPa (8 μm Cu TSV diameter). As such, no conclusive stress dependence on Cu TSV diameter was determined. This is attributed to stress relaxation mechanisms including plastic deformation, grain boundary sliding, dislocation motion and the formation of cracks/ voids which are otherwise neglected in many reported finite element modeling based studies. Additionally, this study underscores that the stress-strain behavior of Cu TSVs are significantly dependent on their thermal history and microstructural characteristics. |
| Starting Page | 54 |
| Ending Page | 58 |
| File Size | 1108700 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479986095 |
| DOI | 10.1109/ECTC.2015.7159571 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stress Through-silicon vias Stress measurement Annealing Microstructure Strain Semiconductor device measurement |
| Content Type | Text |
| Resource Type | Article |
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