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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sungwook Moon Jinho Kim Jihyun Lee Taeyong Kim Kyongho Kim |
| Copyright Year | 2015 |
| Description | Author affiliation: Syst. LSI Bus. Div., Samsung Electron. Co. Ltd., Hwaseong, South Korea (Sungwook Moon; Jinho Kim; Jihyun Lee; Taeyong Kim; Kyongho Kim) |
| Abstract | Inside an electronic product with high-speed interfaces, a lot of technological effort is required for neutralizing mutual electromagnetic interference (EMI) between adjacent electronic components. Thus, it is necessary to adopt an EMI-aware design to maintain high-performance features by avoiding possible EMI causes in a large-scale integration (LSI) chip. In this work, we analyzed IC-level EMI causes for improving on-chip EMI perspectives by characterizing composing channel impedance with a view to the whole system. A test channel for characterizing system-level impedance properties consists of power/ground nets of on-chip metal layers, a chip-on film (CoF), and a printed circuit board (PCB). Specifically, we compared two test samples with different features. One (sample 1) has a 0.8nF on-chip decoupling capacitor, only horizontal Vdd-Vss pairing layout for power interconnects, and 0.2T clock shift scheme from data edge position. The other (sample 2) has a 1.5nF on-chip decoupling capacitor, both vertical and horizontal Vdd-Vss pairing layout for confining an EM field, and 0.5T clock shift scheme for frequency spreading effect. Using simulation results and frequency domain analysis, the impedance was found to be 1.3 Ohm to 0.9 Ohm at a specific noise frequency of interest (132MHz) as the decoupling capacitance increases from 0.8 nF to 1.5nF. In comparison, the performance of EMI properties in sample 2 was found to be improved by 6.0dB when compared to sample1. Specifically, this improvement turned out to be affected by 3.2dB due to increasing on-chip decoupling capacitance of 0.7dB due to a shielding effect on the power/ground interconnect layout of an added metal layer and 1.6dB due to changing the scheme of a clock timing transition. In the simulation-based estimation, this 5.5dB improvement was demonstrated to agree with the near-field measurement with a 6.0dB improvement. Consequently, our approach to analyze on-chip EMI effects is helpful to understand complex electromagnetic behaviors in an LSI chip and it is also expected to be applicable in suppressing complex EMI causes for leveraging on-chip EMI performance. |
| Starting Page | 757 |
| Ending Page | 761 |
| File Size | 1308733 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479986095 |
| DOI | 10.1109/ECTC.2015.7159677 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Electromagnetic interference System-on-chip Clocks Layout Magnetic field measurement Noise Impedance |
| Content Type | Text |
| Resource Type | Article |
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