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Content Provider | IEEE Xplore Digital Library |
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Author | Yu-Hua Chen Dyi-Chung Hu Tzvy-Jang Tseng |
Copyright Year | 2015 |
Description | Author affiliation: Unimicron Technol. Corp., Hsinchu, Taiwan (Yu-Hua Chen; Dyi-Chung Hu; Tzvy-Jang Tseng) |
Abstract | For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, managing the substrate warpage along processing steps becomes critical. Thin organic substrates face challenging warpage issues in manufacture and in chip assembly. Glass is one of the candidates that can be used in substrate to replace traditional organic substrate. The infrastructure of glass for LCD industry has already been developed for many years. Glass also has several superior properties than other substrate candidates, such as large panel size availability, adjustable CTE, high modulus, low dielectric constant, low dielectric loss and high insulating capability. Glass represents an attractive choice with potential of tailorable properties dependent on specific glass composition. By targeting the coefficient of thermal expansion (CTE), the CTE of glass can be made to match perfectly with silicon dies and for reliable package. In addition, the advantages of using glass for interposer derive from process flexibility for size and thickness since the glass fusion process provides sheets with dimensions of more than three meters. It is straight forward to provide glass substrate of almost any size needed. Large glass panels are ideally suited for fabrication of interposer where the panel process is expected to provide large number of interposers in each run compared with wafer processing. In addition, the two sided processing of the panel, the avoidance of CMP processes and without using liners further enable lower unit cost for the interposer. This paper demonstrates fabrication of glass interposer with through glass vias (TGV) daisy chain test vehicles using a 20” x 20” (508mm x 508mm) panel size glass substrate manufactured by substrate HVM (high volume manufacture) line for 2.5D SiP application. Daisy chain electrical measurement results of this glass substrate demonstrated good continuity and electric resistance. The reliability test results will also be described including pre-condition and thermal cycle test (TCT). |
Starting Page | 1610 |
Ending Page | 1615 |
File Size | 1353367 |
Page Count | 6 |
File Format | |
ISBN | 9781479986095 |
DOI | 10.1109/ECTC.2015.7159812 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2015-05-26 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Glass Substrates Vehicles Reliability Fabrication Silicon Accuracy |
Content Type | Text |
Resource Type | Article |
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