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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pares, G. Karoui, C. Zaid, A. Dosseul, F. Feron, M. Attard, A. Klug, G. Luesebrink, H. Martinschitz, K. Launay, N. Belhenini, S. Simon, G. |
| Copyright Year | 2013 |
| Description | Author affiliation: BESI Austria GmbH, Radfeld, Austria (Attard, A.) || SPTS, Annecy le Vieux, France (Launay, N.) || MINATEC, CEA-LETI, Grenoble, France (Pares, G.; Simon, G.) || DISCO HI-TEC Eur. GmbH, Kirchheim, Germany (Klug, G.) || EV Group E. Thallner GmbH, St. Florian am Inn, Austria (Martinschitz, K.) || LMR, Tours, France (Belhenini, S.) || STMicroelectron. Tours SAS, Tours, France (Karoui, C.; Zaid, A.; Dosseul, F.; Feron, M.) || PVA TePla AG, Kirchheim, Germany (Luesebrink, H.) |
| Abstract | This work aims at answering to the 3D mega trend of silicon based platform and 3D wafer level packaging (3D-WLSiP). We focus on the development of architectures compliant with high volume markets for applications like mobile telecommunication. In this market, the silicon material will remain the key platform for 3D integration and has to offer the vertical interconnection as well as ultra-thin packages to fit into very slim electronic devices. We have designed both a mechanical demonstrator with daisy chains and a fully functional product based on a silicon interposer, focusing on forward and backward compatibility between Front-End and 3D packaging and the development of a complete set of advanced technological modules: - Thru-silicon-via interconnections (TSV) with copper via-mid technologies. - Ultra-thin (20 and 35 μm) chips fabrication using dicing before grinding (DBG) with 45° beveled edge and plasma stress release technology. - Thin chips stack on the TSV interposer before processing the back side (stacking first) with two different approaches. The first one is a flip chip integration based on Cu/SAC μ-bumps while the second is the Back-to-Face (B2F) way based on high topology RDL after permanent bonding of the chips face up on the interposer. Chip bonding is done with several materials either on die side with die attach film (DAF) or on interposer side using wafer level spin coated polymers. - Thin wafer handling using advanced temporary bonding process to handle the thin silicon interposer wafers during the integration based on BSI product from Brewer Science and ZoneBOND™ technology. Moreover different strategies of handling have been investigated involving high topology temporary bonding as well as carrier flip-flop approaches. - Thin wafer level packaging (TWLP) has been implemented sequentially on front side and back side of the thin resulting in a fully 3D-WLSiP module. Thermo-mechanical FEM simulation and first reliability assessment using mechanical demonstrator have been carried out and support the good mechanical behaviour of the integration. Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnection schemes in terms of resistances and yield at front side level but also at back side level after TSV exposure, RDL and bumps. Successful results of development loops have led to start processing a full functional product benefiting of the best process flow. |
| Sponsorship | IEEE Components, Packaging Manuf. Technol. Soc. |
| Starting Page | 305 |
| Ending Page | 306 |
| File Size | 3583875 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479902330 |
| ISSN | 05695503 |
| e-ISBN | 9781479902323 |
| DOI | 10.1109/ECTC.2013.6575588 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-05-28 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Through-silicon vias Copper Bonding Stacking Silicon Topology Packaging |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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