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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ren-Shin Cheng Yin-Po Hung Tzu-Ying Kuo Yu-Min Lin Fan-Jun Leu Tao-Chih Chang |
| Copyright Year | 2013 |
| Description | Author affiliation: Ind. Technol. Res. Inst., Hsinchu, Taiwan (Ren-Shin Cheng; Yin-Po Hung; Tzu-Ying Kuo; Yu-Min Lin; Fan-Jun Leu; Tao-Chih Chang) |
| Abstract | In the evolution of IC package, the primary trend is regarded to be the upgrading from planar 2D integration to 3D stacking. But before stepping into 3D IC category, a transitional generation called 2.5D is proposed. Due to the extremely fine pitch of modern IC, the IC substrate is difficult to match due to the incomparable line width/space. Therefore, a silicon interposer is introduced to fulfill the requirement of circuit re-distribution. In this paper, a package structure contains Si interposer to meet the demand of smaller and thinner form factor is proposed. The interposer is embedded into substrate by means of dielectric material lamination rather than solders joining and flip chip bonding. The embedded packaging technology is an integration of embedding active and passive components in built-up substrates and printed circuit boards (PCB). It can also be regarded as a process integration of PCB substrate and silicon substrate that raised the package density and miniaturized the package volume. In this investigation, an 8 inch thinned wafer was used as the test vehicle. Through silicon vias (TSVs) for interconnection could be produced either by deep reactive ion etching (DRIE) at wafer-level or by laser drilling at chiplevel. Meanwhile, Si chips were interconnected to the Si interposer to form an integrated 2.5D module. Afterwards, the 2.5D module was embedded by laminating a dielectric layer on both side of the module. Subsequently, the UV laser was used to form blind vias on the dielectric layer, and the chemical processes including de-smear, seed layer coating, Cu plating were applied to form the circuits or the BGA pads on the top or the bottom surface of build-up layer to connect the circuits of the 2.5D module. After circuit forming, the dielectric layer was fully cured at 170°C to enhance the adhesion between the Cu trace and the dielectric material. With this architecture, the thickness of interposer in a 2.5D-SiP could be subtracted, and the electrical performance should be improved because of a shorter signal transmission route. The feasibility of the packaging structure has been verified. The reliability is assessing by preconditioning, and the results were also discussed here. |
| Sponsorship | IEEE Components, Packaging Manuf. Technol. Soc. |
| Starting Page | 1975 |
| Ending Page | 1979 |
| File Size | 1658813 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479902330 |
| ISSN | 05695503 |
| e-ISBN | 9781479902323 |
| DOI | 10.1109/ECTC.2013.6575849 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-05-28 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon Integrated circuits Stress Lamination Strain Substrates Reliability |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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