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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hariharan, G. Chaware, R. Yip, L. Singh, I. Ng, K. Pai, S.Y. Myongseob Kim Liu, H. Ramalingam, S. |
| Copyright Year | 2013 |
| Description | Author affiliation: Xilinx, Inc., San Jose, CA, USA (Hariharan, G.; Chaware, R.; Yip, L.; Singh, I.; Ng, K.; Pai, S.Y.; Myongseob Kim; Liu, H.; Ramalingam, S.) |
| Abstract | This paper presents results for assembly and reliability evaluations performed while developing a first of its kind heterogeneous 2.5D HiCTE Ceramic Field Programmable Gate Array (FPGA) package. The heterogeneous device discussed here is a three dimensionally stacked FPGA device integrated with a 28G Transceiver die using a passive interposer. Several thousands of micro bumps are used for making connections between the FPGA die slices and the 28G transceiver through a passive interposer. Such heterogeneous integration enables ultra-high inter-die bandwidth and capacity at very low power that are essential for meeting the growing demands in the communication space. Also, it helps in achieving a much lower latency. The selection of ceramic substrates makes this three dimensional stacking very unique as its behavior at high temperature is very different from its organic counterparts. The Assembly test vehicles comprised of two 28nm FPGA Die and one 28nm Transceiver Die, all stacked side by side on a 25 mm × 20mm interposer. The FPGA and Interposer assembly was stacked on a 35mm × 35mm Ceramic Substrate with 180μm pitch C4 bumps. Assembly evaluations were primarily focused on qualifying various materials and assembly processes to enable a heterogeneous stacked silicon assembly on a ceramic substrate. Micro bump joint quality, assembly yield, component level reliability and board level reliability have been used as the key gating items for this process qualification study. Two different assembly processes, namely thermo-compression (TC) bonding and mass reflow, were compared during this evaluation. Component and board level reliability evaluations were carried out for various assembly and material combinations. The assembled units were subjected to Level 4 (L4) preconditioning test followed by -55°C to 125 °C thermal regimes and tested for functionality to monitor the component level reliability. Board level studies were conducted at 0°C to 100 °C using daisy chain substrates. The resistance of the BGA chain was used for monitoring the board level reliability. The results of this evaluation have clearly demonstrated a strong interaction between the materials, assembly process and reliability. The choice of the assembly process was observed to have a significant impact on the micro bump joint quality. However, the choice of the assembly process itself was dependent on the selection of the various assembly materials including underfill, flux, substrate type, surface finish, lid thickness and die thickness. The assembly process and material set together influenced the component and board level reliability significantly. |
| Sponsorship | IEEE Components, Packaging Manuf. Technol. Soc. |
| Starting Page | 904 |
| Ending Page | 908 |
| File Size | 679027 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479902330 |
| ISSN | 05695503 |
| e-ISBN | 9781479902323 |
| DOI | 10.1109/ECTC.2013.6575681 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-05-28 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Reliability Substrates Assembly Ceramics Field programmable gate arrays Joints |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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