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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lewis, B.J. Baldwin, D.F. Houston, P.N. Fei Xie Le Hang La |
| Copyright Year | 2013 |
| Description | Author affiliation: Adv. Assembly Technol., Engent, Inc. - Enabling Next Generation Technol., Norcross, GA, USA (Lewis, B.J.; Baldwin, D.F.; Houston, P.N.; Fei Xie; Le Hang La) |
| Abstract | Commonly, during the process development cycle for new products, limitations exist on the materials that are available for the prototype work. Most SMT devices are readily available in different formats and solder alloys to satisfy most of the needs for passive components, however, many times, IC devices are limited to what is available from the fab or IC brokers. These limitations range from die only available with aluminum, wirebond ready I/O metallization, pad layouts in fine pitch perimeter patterns or that the silicon wafers are already sawn and presented as singulated die. For applications where advancement in performance or miniaturization is needed, and the benefits of flip chip technology are attractive, it is not a trivial task to be able to use these die. In these cases, the process of adding solderable plating technologies to the I/O bond pads is very favorable. The technologies are currently run for wafer lever plating baths, but very little has been done to evaluate singulated chip plating. Work in plating Ni/Pd onto the ALCAP structure has been performed to evaluate the process and feasibility of processing groups of singulated die with aluminum bond pads. The work to be detailed in this paper will go through the chemistries used in the plating process onto an aluminum bond pad that makes it suitable for flip chip processes. Several bumping structures, such as solder bumping over this Ni/Pd plating stack up and plating over gold or copper stud bumps before adding solder bumps, are evaluated. A process for low cost bumping the singulated flip chips is also detailed. The data for shear testing of 10 variations of bumping structures, before and after 500 liquid thermal shock cycles, is detailed. Finally, a comprehensive study for assembly of solder bumped flip chips, with the various selective plating processes, will be detailed as well as a detailed analysis of the TC reliability of this assembly approach. It will be shown that selective Ni/Pd plating onto singulated, ALCAP bare die can allow, for these die that are typically wire bonded, to be used in a practical approach, solder flip chip process. It will also be shown that these processes provide reasonable reliability results when compared to a mainstream, wafer processed, solder bumped flip chip die. |
| Sponsorship | IEEE Components, Packaging Manuf. Technol. Soc. |
| Starting Page | 1564 |
| Ending Page | 1568 |
| File Size | 1794281 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479902330 |
| ISSN | 05695503 |
| e-ISBN | 9781479902323 |
| DOI | 10.1109/ECTC.2013.6575780 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-05-28 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Nickel Flip-chip devices Gold Assembly Copper Testing Surface treatment |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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