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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Vempati, S.R. Su, N. Chee Houe Khong Ying Ying Lim Vaidyanathan, K. Lau, J.H. Liew, B.P. Au, K.Y. Tanary, S. Fenner, A. Erich, R. Milla, J. |
| Copyright Year | 2009 |
| Description | Author affiliation: UTAC, Packaging and Assembly Technology, 5 Serangoon North Ave 5, Singapore 554916 (Liew, B.P.; Au, K.Y.; Tanary, S.) || MMC, 2343 W. Medtronic Way, Tempe AZ 85281, USA (Fenner, A.; Erich, R.; Milla, J.) || Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Vempati, S.R.; Su, N.; Chee Houe Khong; Ying Ying Lim; Vaidyanathan, K.; Lau, J.H.) |
| Abstract | Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies. Face-to-face silicon (Si) dies stacking is one of the three dimensional (3D) packaging technologies to form a high density module. In this work, a chip level stacked module was demonstrated for medical application and assessed its package level reliability. The chip level stack module is achieved by stacking two thin dies of different size and thickness together using flip chip technology with micro bump interconnects. Electrical simulations are carried out to obtain RLC parameters of micro bump interconnect and complete interconnection from daughter die to substrate. Mechanical simulations are also carried out to study the stress analysis on micro bumps and CSP bumps in the package and parametric study of stacked module package to study the effect of substrate material, underfill material die thicknesses on package reliability and warpage. Test chips are designed and fabricated with daisy chain test structures to access the reliability of the stack module. Pb-free (SnAg) micro bumps of 40 µm on daughter die wafers and Eutectic SnPb solder CSP bumps of 200 µm height on Mother die wafers are fabricated. Mother die and daughter die bumped wafers were thinned to 300 µm and 60 µm respectively using mechanical backgrinding method. These thin dies are stacked using chip to wafer flip chip bonding and underfill process is established for the micro bump interconnects. The assembled Si die stacked modules are subjected to JEDEC package level reliability tests in terms of temperature cycle test (TC), high temperature storage test (HTS), moisture sensitivity test level 1 (MST L1) and MST L3, and un-biased High accelerated stress test (uHAST) and results are presented. |
| Starting Page | 980 |
| Ending Page | 987 |
| File Size | 2573638 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424444755 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2009.5074132 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-05-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon Flip chip Testing Stacking Stress Chip scale packaging Temperature sensors Lead Medical services Biomedical equipment |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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