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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Murugesan, M. Bea, J.-C. Fukushima, T. Konno, T. Kiyoyama, K. Jeong, W.-C. Kino, H. Noriki, A. Lee, K.-W. Tanaka, T. Koyanagi, M. |
| Copyright Year | 2009 |
| Description | Author affiliation: Dept. of Bioengineering and Robotics, Tohoku Univ., 6-6-01 Aza Aoba, Aramaki, Aoba-ku, Sendai, 980-8579, Japan (Murugesan, M.; Bea, J.-C.; Fukushima, T.; Konno, T.; Kiyoyama, K.; Jeong, W.-C.; Kino, H.; Noriki, A.; Lee, K.-W.; Tanaka, T.; Koyanagi, M.) |
| Abstract | A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were fabricated via conventional electroplating technique. As formed single as well as daisy chain lateral interconnects (both are crossing over the thick test chips that are face-up bonded onto the flexible substrates by self-assembly) were characterized for their electrical characteristics. We have obtained a low resistance values for the Cu lateral interconnects which are close to the calculated values. Further, a module contains RF test chips that are interconnected by this unique Cu lateral interconnections has been tested for the operation. |
| Starting Page | 1496 |
| Ending Page | 1501 |
| File Size | 4492525 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424444755 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2009.5074210 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-05-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Bonding Wire Copper Through-silicon vias Substrates Stacking Temperature Large scale integration Packaging Automatic testing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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