NDLI: Obstacle-avoiding free-assignment routing for flip-chip designs

Content Provider	IEEE Xplore Digital Library
Author	Po-Wei Lee Hsu-Chieh Lee Yuan-Kai Ho Yao-Wen Chang Chen-Feng Chang I-Jye Lin Chin-Fang Shen
Copyright Year	2012
Description	Author affiliation: Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan (Po-Wei Lee; Hsu-Chieh Lee; Yuan-Kai Ho; Yao-Wen Chang) \|\| Synopsys Inc., Taipei 110, Taiwan (Chen-Feng Chang; I-Jye Lin; Chin-Fang Shen)
Abstract	The flip-chip packaging is introduced for modern IC designs with higher integration density and larger I/O counts. It is necessary to consider routing obstacles for modern flip-chip designs, where the obstacles could be regions blocked for signal integrity protection (especially for analog/mixed-signal modules), pre-routed or power/ground nets, and even for through-silicon vias for 3D IC designs. However, no existing published works consider obstacles. To remedy this insufficiency, this paper presents the first work to solve the free-assignment flip-chip routing problem considering obstacles. For the free-assignment routing problem, most existing works apply the network-flow formulation. Nevertheless, we observe that no existing network-flow model can exactly capture the routability of a local routing region (tile) in presence of obstacles. This paper presents the first work that can precisely model the routability of a tile, even with obstacles. Based on this new model, a two-stage approach of global routing followed by detailed routing is proposed. The global routing computes a routing topology by the minimum-cost maximum-flow algorithm, and the detailed routing determines the precise wire positions. Dynamic programming is applied to further merge tiles to reduce the problem size. Compared to a state-of-the-art flow model with obstacle handling extensions, experimental results show that our algorithm can achieve 100% routability for all circuits while the extensions of the previous work cannot complete routing for any benchmark circuit with obstacles.
Starting Page	1088
Ending Page	1093
File Size	493238
Page Count	6
File Format	PDF
ISBN	9781450311991
ISSN	0738100X
e-ISBN	9781450311991
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Tiles Routing Wires Merging Wiring Computational modeling Integrated circuits Obstacle-avoiding Physical design Flip-chip routing Free-assignment
Content Type	Text
Resource Type	Article

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