NDLI: DAE2FSM: Automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics

Content Provider	IEEE Xplore Digital Library
Author	Aadithya, K.V. Roychowdhury, J.
Copyright Year	2012
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA (Aadithya, K.V.; Roychowdhury, J.)
Abstract	We abstract the I/O functionality of continuous-time dynamical systems (e.g., SPICE netlists with combinational and sequential logic) as Finite State Machines (FSMs). This enables efficient simulation of large designs implemented with less-than-perfect devices and components, and also opens the door to formal verification of transistor-level designs against higher-level specifications. In particular, our automatically generated FSMs faithfully capture the behaviour of latches, flip-flops, and circuits constructed from them. Among other technical advances, we generalize an existing (binary-only) FSM-learning approach to arbitrary I/O alphabets, which empowers it to learn high-fidelity abstractions of multi-level-discretized, multi-input/multi-output systems. Our approach, when applied to correctly functioning latches and flip-flops, is able to learn compact, multi-input FSM abstractions whose predictions closely match SPICE simulations. In addition, we have also applied our technique to produce multi-level-discretized FSM representations of digital systems that nevertheless exhibit "analogish" traits, such as an over-clocked, error-prone D-flip-flop. For such circuits, the automatically learned FSM abstraction includes additional states that characterise "failure modes" of the circuit for specific input sequences (these failure modes are also confirmed by SPICE simulations). Finally, we demonstrate that our technique is also applicable to larger and more complex multi-input, multi-output systems; for example, we are able to automatically derive an accurate FSM abstraction of a 280-transistor (BSIM4), 0-to-5 increment/decrement counter.
Starting Page	311
Ending Page	316
File Size	1483734
Page Count	6
File Format	PDF
ISBN	9781450311991
ISSN	0738100X
e-ISBN	9781450311991
DOI	10.1145/2228360.2228418
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Clocks Latches SPICE Switches Delay Machine learning Integrated circuit modeling Circuit Simulation Finite State Machine Learning
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

DAE2FSM: automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics

Behavioral modeling of continuous time /spl Delta//spl Sigma/ modulators

Automatic clock tree design with IPs in the system

Data Parallel Simulation Using Time-Warp on the Connection Machine

Automatic scan insertion and pattern generation for asynchronous circuits

Buying time for the stuck-at fault model

A 2500-gate bipolar macro cell array with 250ps gate delay

TITAN: An Universal Circuit Simulator with Event Control for Latency Exploitation

CMOS circuit speed optimization based on switch level simulation

DAE2FSM: Automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics

Similar Documents

DAE2FSM: automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics

Behavioral modeling of continuous time /spl Delta//spl Sigma/ modulators

Automatic clock tree design with IPs in the system

Data Parallel Simulation Using Time-Warp on the Connection Machine

Automatic scan insertion and pattern generation for asynchronous circuits

Buying time for the stuck-at fault model

A 2500-gate bipolar macro cell array with 250ps gate delay

TITAN: An Universal Circuit Simulator with Event Control for Latency Exploitation

CMOS circuit speed optimization based on switch level simulation

DAE2FSM: Automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics