NDLI: GLARE: Global and local wiring aware routability evaluation

Content Provider	IEEE Xplore Digital Library
Author	Yaoguang Wei Sze, C. Viswanathan, N. Zhuo Li Alpert, C.J. Reddy, L. Huber, A.D. Tellez, G.E. Keller, D. Sapatnekar, S.S.
Copyright Year	2012
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA (Yaoguang Wei; Sapatnekar, S.S.) \|\| IBM Austin Research Lab, Austin, TX, USA (Sze, C.; Zhuo Li; Alpert, C.J.) \|\| IBM Systems and Technology Group, Austin, TX, USA (Viswanathan, N.) \|\| IBM Systems and Technology Group, Hopewell Junction, NY, USA (Reddy, L.; Huber, A.D.; Keller, D.) \|\| IBM Systems and Technology Group, Burlington, VT, USA (Tellez, G.E.)
Abstract	Industry routers are very complex and time consuming, and are becoming more so with the explosion in design rules and design for manufacturability requirements that multiply with each technology node. Global routing is just the first phase of a router and serves the dual purpose of (i) seeding the following phases of a router and (ii) evaluating whether the current design point is routable. Lately, it has become common to use a “light mode” version of the global router, similar to today's academic routers, to quickly evaluate the routability of a given placement. This use model suffers from two primary weaknesses: (i) it does not adequately model the local routing resources, while the model is important to remove opens and shorts and eliminate DRC violations, (ii) the metrics used to represent congestion are non-intuitive and often fail to pinpoint the key issues that need to be addressed. This paper presents solutions to both issues, and empirically demonstrates that incorporating the proposed solutions within a global routing based congestion analyzer yields a more accurate view of design routability.
Starting Page	768
Ending Page	773
File Size	1440377
Page Count	6
File Format	PDF
ISBN	9781450311991
ISSN	0738100X
e-ISBN	9781450311991
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Routing Measurement Analytical models Steiner trees Pins Estimation Accuracy Congestion metric Physical design Routability evaluation Local wiring modeling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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