NDLI: Incremental power grid verification

Content Provider	IEEE Xplore Digital Library
Author	Abhishek Najm, F.N.
Copyright Year	2012
Description	Author affiliation: ECE Dept., Univ. of Toronto, Toronto, ON, Canada (Abhishek; Najm, F.N.)
Abstract	Verification of the on-die power grid is a key step in the design of complex high-performance integrated circuits. For the very large grids in modern designs, incremental verification is highly desirable, because it allows one to skip the verification of a certain section of the grid (internal nodes)and instead, verify only the rest of the grid (external nodes). We propose an efficient approach for incremental verification in the context of vectorless constraints-based grid verification, under dynamic conditions. The traditional difficulty is that the dynamic case requires iterative analysis of both the internal and external sections. This has been previously overcome for simulation purposes, but we provide the first solution for verification, through two key contributions: 1)a bound on the internal nodes' voltages is developed that eliminates the need for iterative analysis, and 2)a multi-port Norton approach is used to construct a reduced macromodel for the internal section. As a result, we demonstrate significant reductions in runtime, with speed-ups in the range of 3-8×, with negligible impact on accuracy.
Starting Page	151
Ending Page	156
File Size	392440
Page Count	6
File Format	PDF
ISBN	9781450311991
ISSN	0738100X
e-ISBN	9781450311991
DOI	10.1145/2228360.2228390
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Power grids Upper bound Vectors Symmetric matrices Integrated circuit modeling Mathematical model Equations voltage drop Power Grid
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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