NDLI: Early prediction of NBTI effects using RTL source code analysis

Content Provider	IEEE Xplore Digital Library
Author	Kumar, J.A. Butler, K.M. Heesoo Kim Vasudevan, S.
Copyright Year	2012
Description	Author affiliation: Texas Instrum. Inc., Dallas, TX, USA (Butler, K.M.) \|\| Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA (Kumar, J.A.; Heesoo Kim; Vasudevan, S.)
Abstract	In present day technology, the design of reliable systems must factor in temporal degradation due to aging effects such as Negative Bias Temperature Instability (NBTI). In this paper, we present a methodology to estimate delay degradation early at the Register Transfer Level (RTL). We statically analyze the RTL source code to determine signal correlations. We then determine probability distributions of RTL signals formally by using probabilistic model checking. Finally, we propagate these signal probabilities through delay macromodels and estimate the delay degradation. We demonstrate our methodology on several benchmarks RTL designs. We estimate the degradation with <;10% error and up to 18.2× speedup in runtime as compared to estimation using gate-level simulations.
Starting Page	808
Ending Page	813
File Size	382763
Page Count	6
File Format	PDF
ISBN	9781450311991
ISSN	0738100X
e-ISBN	9781450311991
DOI	10.1145/2228360.2228506
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Delay Logic gates Degradation Computational modeling Probabilistic logic Reliability Aging Static Analysis NBTI Statistical Analysis RTL
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Early prediction of NBTI effects using RTL source code analysis

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Hierarchical identification of NBTI-critical gates in nanoscale logic

TG-based technique for NBTI degradation and leakage optimization

An age-aware library for reliability simulation of digital ICs

NBTI-aware statistical timing analysis framework

Failure Analysis of Asymmetric Aging Under NBTI

Circuit characteristic analysis considering NBTI and PBTI-induced delay degradation

Controlling NBTI degradation during static burn-in testing

Early prediction of NBTI effects using RTL source code analysis

Similar Documents

Early prediction of NBTI effects using RTL source code analysis

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Hierarchical identification of NBTI-critical gates in nanoscale logic

TG-based technique for NBTI degradation and leakage optimization

An age-aware library for reliability simulation of digital ICs

NBTI-aware statistical timing analysis framework

Failure Analysis of Asymmetric Aging Under NBTI

Circuit characteristic analysis considering NBTI and PBTI-induced delay degradation

Controlling NBTI degradation during static burn-in testing

Early prediction of NBTI effects using RTL source code analysis