NDLI: Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

Content Provider	IEEE Xplore Digital Library
Author	Moongon Jung Pan, D.Z. Sung Kyu Lim
Copyright Year	2012
Description	Author affiliation: School of ECE, Georgia Institute of Technology, Atlanta, GA, USA (Moongon Jung; Sung Kyu Lim) \|\| Department of ECE, University of Texas at Austin, Austin, TX, USA (Pan, D.Z.)
Abstract	In this work, we propose a fast and accurate chip/package thermo-mechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization methodology to alleviate mechanical reliability issues in 3D IC. First, we analyze the stress induced by chip/package interconnect elements, i.e., TSV, μ-bump, and package bump. Second, we explore and validate the principle of lateral and vertical linear superposition of stress tensors (LVLS), considering all chip/package elements. This linear superposition principle is utilized to perform full-chip/package-scale stress simulations and reliability analysis. Finally, we study the mechanical reliability issues in practical 3D chip/package designs including wide-I/O and block-level 3D ICs.
Starting Page	317
Ending Page	326
File Size	2281325
Page Count	10
File Format	PDF
ISBN	9781450311991
ISSN	0738100X
e-ISBN	9781450311991
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Through-silicon vias Reliability Tensile stress Substrates chip/package co-analysis 3D IC TSV stress mechanical reliability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

Design for manufacturability and reliability for TSV-based 3D ICs

Thermomechanical reliability challenges induced by high density Cu TSVs and metal micro-joining for 3-D ICs

An accurate semi-analytical framework for full-chip TSV-induced stress modeling

A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

Similar Documents

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

Design for manufacturability and reliability for TSV-based 3D ICs

Thermomechanical reliability challenges induced by high density Cu TSVs and metal micro-joining for 3-D ICs

An accurate semi-analytical framework for full-chip TSV-induced stress modeling

A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs