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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jin-Tai Yan Yu-Jen Tseng Chia-Heng Yen |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Comput. Sci. & Inf. Eng., Chung-Hua Univ., Hsinchu, Taiwan (Jin-Tai Yan; Yu-Jen Tseng) || Dept. of Comput. Sci. & Eng., Nat. Taiwan Ocean Univ., Keelung, Taiwan (Chia-Heng Yen) |
| Abstract | It is well known that single-layer routing is used for RDL routing in flip-chip designs and substrate routing in package designs. In this paper, given a set of two-terminal nets in a single-layer gridded routing plane, the routing regions of all the given nets can be initially constructed. Based on the routing constraints on different intersection conditions of two routing regions in a single layer, the wiring directions of the given nets can be further assigned. Finally, based on the assigned directions of the given nets, the wiring paths of the given nets onto the routing grids can be assigned by diffusing the overlapping paths and eliminating the unnecessary detours in single-layer routing. The experimental results show that our proposed approach can route 99.98% of the given nets in single-layer routing for 6 tested examples in reasonable CPU time on the average. |
| Sponsorship | IEEE Circuits Syst. Soc. |
| Starting Page | 393 |
| Ending Page | 396 |
| File Size | 546605 |
| Page Count | 4 |
| File Format | |
| e-ISBN | 9781479934324 |
| DOI | 10.1109/ISCAS.2014.6865148 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-06-01 |
| Publisher Place | Australia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Routing Wiring Shape Substrates Flip-chip devices Design automation Integrated circuits |
| Content Type | Text |
| Resource Type | Article |
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