NDLI: Heterogeneous multi-channel: Fine-grained DRAM control for both system performance and power efficiency

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2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

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DAC Design Automation Conference 2012

Executive committee

General chair's message

Perspective paper abstracts [3 abstracts]

Table of contents

Technical panel abstracts

My First Design Automation Conference - 1982 [Thursday keynote address]

Scaling for 2020 Solutions [Tuesday keynote address]

Designing High Performance Systems-on-Chip [Wednesday keynote address]

Biomedical electronics serving as physical environmental and emotional watchdogs

Integrated biosensors for personalized medicine

Design challenges for secure implantable medical devices

Design of pin-constrained general-purpose digital microfluidic biochips

Path scheduling on digital microfluidic biochips

Realizing reversible circuits using a new class of quantum gates

Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors

A semiempirical model for wakeup time estimation in power-gated logic clusters

Cost-effective power delivery to support per-core voltage domains for power-constrained processors

A hybrid and adaptive model for predicting register file and SRAM power using a reference design

Coding-based energy minimization for Phase Change Memory

A code morphing methodology to automate power analysis countermeasures

Security analysis of logic obfuscation

Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry

On improving the uniqueness of silicon-based physically unclonable functions via Optical Proximity Correction

Transformer: A functional-driven cycle-accurate multicore simulator

SAGA: SystemC acceleration on GPU architectures

Synchronization for hybrid MPSoC full-system simulation

A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation

Can EDA combat the rise of electronic counterfeiting?

Physics matters: Statistical aging prediction under trapping/detrapping

Library-aware resonant clock synthesis (LARCS)

Incremental power grid verification

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs

Tracking appliance usage information in residential settings using off-the-shelf low-frequency meters

Implementing an FPGA system for real-time intent recognition for prosthetic legs

Statistical design and optimization for adaptive post-silicon tuning of MEMS filters

Generic low-cost characterization of VTH and mobility variations in LTPS TFTs for non-uniformity calibration of active-matrix OLED displays

Towards fault-tolerant embedded systems with imperfect fault detection

Steady-state dynamic temperature analysis and reliability optimization for embedded multiprocessor systems

Considering diagnosis functionality during automatic system-level design of automotive networks

Meta-Cure: A reliability enhancement strategy for metadata in NAND flash memory storage systems

EDA for secure and dependable cybercars: Challenges and opportunities

Software controlled cell bit-density to improve NAND flash lifetime

Observational wear leveling: An efficient algorithm for flash memory management

Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs

Point and discard: A hard-error-tolerant architecture for non-volatile last level caches

Self-aware computing in the Angstrom processor

The case for elastic operating system services in fos

A compiler and runtime for heterogeneous computing

The HELIX project: Overview and directions

Exploring sub-20nm FinFET design with Predictive Technology Models

Fast nonlinear model order reduction via associated transforms of high-order Volterra transfer functions

AMOR: An efficient aggregating based model order reduction method for many-terminal interconnect circuits

BLAST: Efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric lagrange enabled transient adjoint analysis

DAE2FSM: Automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

Symbolic model checking on SystemC designs

System verification of concurrent RTL modules by compositional path predicate abstraction

Equivalence checking for behaviorally synthesized pipelines

Proving correctness of regular expression accelerators

Sciduction: Combining induction, deduction, and structure for verification and synthesis

Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces

Attackboard: A novel dependency-aware traffic generator for exploring NoC design space

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Explicit modeling of control and data for improved NoC router estimation

Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service

WCET-centric partial instruction cache locking

Worst-case execution time analysis for parallel run-time monitoring

Conforming the runtime inputs for hard real-time embedded systems

STM concurrency control for embedded real-time software with tighter time bounds

HaVOC: A hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and Non-Volatile Memories

Age-based PCM wear leveling with nearly zero search cost

Algorithms and data structures for fast and good VLSI routing

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing

Rule agnostic routing by using design fabrics

Making non-volatile nanomagnet logic non-volatile

mLogic: Ultra-low voltage non-volatile logic circuits using STT-MTJ devices

Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture

Hardware realization of BSB recall function using memristor crossbar arrays

A methodology for energy-quality tradeoff using imprecise hardware

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon

Near-optimal, dynamic module reconfiguration in a photovoltaic system to combat partial shading effects

Networked architecture for hybrid electrical energy storage systems

A new uncertainty budgeting based method for robust analog/mixed-signal design

Variability-aware, discrete optimization for analog circuits

Efficient multi-objective synthesis for microwave components based on computational intelligence techniques

Non-uniform multilevel analog routing with matching constraints

X-Tracer: A reconfigurable X-tolerant trace compressor for silicon debug

Quick detection of difficult bugs for effective post-silicon validation

Test-data volume optimization for diagnosis

Invariance-based concurrent error detection for Advanced Encryption Standard

Accelerating neuromorphic vision algorithms for recognition

Statistical memristor modeling and case study in neuromorphic computing

Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology

GDRouter: Interleaved global routing and detailed routing for ultimate routability

Standard cell routing via Boolean satisfiability

An efficient algorithm for multi-layer obstacle-avoiding rectilinear Steiner tree construction

Avoiding game over: Bringing design to the next level

PowerField: A transient temperature-to-power technique based on Markov random field theory

EigenMaps: Algorithms for optimal thermal maps extraction and sensor placement on multicore processors

An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring

Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints

Static dataflow with access patterns: Semantics and analysis

Executing synchronous dataflow graphs on a SPM-based multicore architecture

System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC

Courteous cache sharing: Being nice to others in capacity management

A hybrid approach to cyber-physical systems verification

Reliable computing with ultra-reduced instruction set co-processors

Identification of recovered ICs using fingerprints from a light-weight on-chip sensor

Confidentiality Preserving Integer Programming for global routing

Design tools for artificial nervous systems

Dynamic river network simulation at large scale

Humans for EDA and EDA for humans

Application of logic synthesis to the understanding and cure of genetic diseases

Exploiting die-to-die thermal coupling in 3D IC placement

ComPLx: A competitive primal-dual Lagrange optimization for global placement

PADE: A high-performance placer with automatic datapath extraction and evaluation through high-dimensional data learning

Structure-aware placement for datapath-intensive circuit designs

GLARE: Global and local wiring aware routability evaluation

The DAC 2012 routability-driven placement contest and benchmark suite

Removing overhead from high-level interfaces

On the asymptotic costs of multiplexer-based reconfigurability

SALSA: Systematic logic synthesis of approximate circuits

Timing ECO optimization using metal-configurable gate-array spare cells

Early prediction of NBTI effects using RTL source code analysis

Generalized SAT-sweeping for post-mapping optimization

Accuracy-configurable adder for approximate arithmetic designs

Recovery-based design for variation-tolerant SoCs

A hybrid NoC design for cache coherence optimization for chip multiprocessors

Architecture support for accelerator-rich CMPs

A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC

Metronome: Operating system level performance management via self-adaptive computing

Adaptive power management of on-chip video memory for Multiview Video Coding

Heterogeneous multi-channel: Fine-grained DRAM control for both system performance and power efficiency

Joint management of RAM and flash memory with access pattern considerations

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU

Write performance improvement by hiding R drift latency in phase-change RAM

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors

Incorrect systems: It's not the problem, It's the solution

On software design for stochastic processors

What to do about the end of Moore's law, probably!

Obtaining and reasoning about good enough software

Improving gate-level simulation accuracy when unknowns exist

Automated feature localization for hardware designs using coverage metrics

Path directed abstraction and refinement in SAT-based design debugging

Checking architectural outputs instruction-by-instruction on acceleration platforms

Standard cell sizing for subthreshold operation

Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits

Regaining throughput using completion detection for error-resilient, near-threshold logic

Process variation in near-threshold wide SIMD architectures

Run-time power-down strategies for real-time SDRAM memory controllers

Embedding statistical tests for on-chip dynamic voltage and temperature monitoring

Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices

Traffic-aware power optimization for network applications on multicore servers

Alternate hammering test for application-specific DRAMs and an industrial case study

Goal-oriented stimulus generation for analog circuits

TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation

Small delay testing for TSVs in 3-D ICs

Circuit and system design guidelines for ultra-low power sensor nodes

Design exploration of energy-performance trade-offs for wireless sensor networks

Energy harvesting and power management for autonomous sensor nodes

Functional timing analysis made fast and general

Timing analysis with nonseparable statistical and deterministic variations

Reversible statistical max/min operation: Concept and applications to timing

Predicting timing violations through instruction-level path sensitization analysis

A chip-package-board co-design methodology

Obstacle-avoiding free-assignment routing for flip-chip designs

Clock tree synthesis with methodology of re-use in 3D IC

Can pin access limit the footprint scaling?

Yield estimation via multi-cones

Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits

Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners

Sparse LU factorization for parallel circuit simulation on GPU

Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse

Platform 2012, a many-core computing accelerator for embedded SoCs: Performance evaluation of visual analytics applications

Assessing the performance limits of parallelized near-threshold computing

Near-threshold voltage (NTV) design — Opportunities and challenges

Near-threshold operation for power-efficient computing? It depends…

Not so fast my friend: Is near-threshold computing the answer for power reduction of wireless devices?

Accurate process-hotspot detection using critical design rule extraction

Improved tangent space based distance metric for accurate lithographic hotspot classification

Simultaneous flare level and flare variation minimization with dummification in EUVL

A novel layout decomposition algorithm for triple patterning lithography

PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method

Exploiting narrow-width values for process variationtolerant 3-D microprocessors

Hardware synthesis of recursive functions through partial stream rewriting

Chisel: Constructing hardware in a Scala embedded language

Specification and synthesis of hardware checkpointing and rollback mechanisms

Optimizing memory hierarchy allocation with loop transformations for high-level synthesis

A metric for layout-friendly microarchitecture optimization in high-level synthesis

Computer generation of streaming sorting networks

CrowdMine: Towards crowdsourced human-assisted verification

Extracting design information from natural language specifications

Material implication in CMOS: A new kind of logic

Boolean satisfiability using noise based logic

Cognitive computing with spin-based neural networks

Capacitance of TSVs in 3-D stacked chips a problem? Not for neuromorphic systems!

Communication-aware mapping of KPN applications onto heterogeneous MPSoCs

Unrolling and retiming of stream applications onto embedded multicore processors

Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systems

EPIMap: Using Epimorphism to map applications on CGRAs

Instruction scheduling for reliability-aware compilation

Compiling for energy efficiency on timing speculative processors

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Heterogeneous multi-channel: Fine-grained DRAM control for both system performance and power efficiency

Content Provider	IEEE Xplore Digital Library
Author	Guangfei Zhang Huandong Wang Xinke Chen Shuai Huang Peng Li
Copyright Year	2012
Description	Author affiliation: Loongson Corporation, Beijing 100190, China (Guangfei Zhang; Huandong Wang; Xinke Chen; Shuai Huang; Peng Li)
Abstract	We propose a novel architecture of memory controller, called HMC (Heterogeneous Multi-Channel), as an improvement to the previous homogeneous multi-channel memory controller. HMC groups physical DRAM devices into logical sub-ranks with different data bus width, and controls them simultaneously. Employing new proposed memory access algorithm, HMC manages the number of devices involved in a single memory access flexibly, and achieves the best performance/power efficiency. Using four-core multiprogramming workloads, our experimental results show that HMC improves system performance by 27.6% with 24.2% reduction in DRAM power consumption on average.
Starting Page	876
Ending Page	881
File Size	451274
Page Count	6
File Format	PDF
ISBN	9781450311991
ISSN	0738100X
e-ISBN	9781450311991
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Random access memory Benchmark testing Memory management Bandwidth Instruction sets Power demand Data buses Power efficiency Chip multiprocessor DRAM Memory access controller
Content Type	Text
Resource Type	Article

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