NDLI: Networked architecture for hybrid electrical energy storage systems

Content Provider	IEEE Xplore Digital Library
Author	Younghyun Kim Sangyoung Park Naehyuck Chang Qing Xie Yanzhi Wang Pedram, M.
Copyright Year	2012
Description	Author affiliation: Seoul National University, Seoul, Korea (Younghyun Kim; Sangyoung Park; Naehyuck Chang) \|\| University of Southern California, Los Angeles, CA, USA (Qing Xie; Yanzhi Wang; Pedram, M.)
Abstract	A hybrid electrical energy storage (HEES) system that consists of multiple, heterogeneous electrical energy storage (EES) elements is a promising solution to achieve a cost-effective EES system because no storage element has ideal characteristics. The state-of-the-art HEES systems are based on a shared-bus charge transfer interconnect (CTI) architecture. Consequently, they are quite limited in scalability which is a function of the number of EES banks. This paper is the first introduction of a HEES system based on a networked CTI architecture, which is highly scalable and is capable of accommodating multiple, concurrent charge transfers. The paper starts by presenting a router architecture for the networked CTI and an effective on-line routing algorithm for multiple charge transfers. In the proposed algorithm, negotiated congestion (NC) routing for multiple charge transfers is performed and any lack of routing resources is addressed by merging two or more charge transfers while maximizing the overall energy efficiency by setting the optimal voltage level for the shared CTI. Examples of the proposed networked CTI are presented and the efficacy of the routing algorithm is demonstrated on a mesh-grid networked CTI.
Starting Page	522
Ending Page	528
File Size	902394
Page Count	7
File Format	PDF
ISBN	9781450311991
ISSN	0738100X
e-ISBN	9781450311991
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Routing Charge transfer Merging Optimization Computer architecture Field programmable gate arrays System-on-a-chip Routing algorithm Hybrid electrical energy storage Charge transfer interconnect
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Networked architecture for hybrid electrical energy storage systems

Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect

Interconnect routing of embedded FPGAs using standard VLSI routing tools

An Input Buffer Architecture for On-chip Routers

A modular router architecture desgin for Network on Chip

An in-system routing strategy for evolvable hardware programmable platforms

On-Chip Communication in Run-Time Assembled Reconfigurable Systems

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture

A flexible 2-D switched-capacitor FPAA architecture and its mapping algorithm

Networked architecture for hybrid electrical energy storage systems

Similar Documents

Networked architecture for hybrid electrical energy storage systems

Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect

Interconnect routing of embedded FPGAs using standard VLSI routing tools

An Input Buffer Architecture for On-chip Routers

A modular router architecture desgin for Network on Chip

An in-system routing strategy for evolvable hardware programmable platforms

On-Chip Communication in Run-Time Assembled Reconfigurable Systems

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture

A flexible 2-D switched-capacitor FPAA architecture and its mapping algorithm

Networked architecture for hybrid electrical energy storage systems