NDLI: TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

Content Provider	IEEE Xplore Digital Library
Author	Moongon Jung Mitra, J. Pan, D.Z. Sung Kyu Lim
Copyright Year	2011
Description	Author affiliation: School of ECE, Georgia Institute of Technology, Atlanta, USA (Moongon Jung; Sung Kyu Lim) \|\| Department of ECE, University of Texas at Austin, USA (Mitra, J.; Pan, D.Z.)
Abstract	In this work, we propose an efficient and accurate full-chip thermo-mechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermo-mechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the use of the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs. Our experimental results demonstrate the effectiveness of our methodology.
Starting Page	188
Ending Page	193
File Size	1812500
Page Count	6
File Format	PDF
ISBN	9781450306362
ISSN	85644924
e-ISBN	9781450306362
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Through-silicon vias Reliability Tensile stress Three dimensional displays Analytical models Integrated circuit modeling mechanical reliability 3D IC TSV stress
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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