NDLI: DDBDD: Delay-Driven BDD Synthesis for FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Lei Cheng Deming Chen Wong, M.D.F.
Copyright Year	2007
Description	Author affiliation: Univ. of Illinois, Urbana (Lei Cheng) \|\| Univ. of Illinois at Urbana-Champaign, Urbana (Deming Chen; Wong, M.D.F.)
Abstract	In this paper, we target FPGA performance optimization using a novel BDD (binary decision graph)-based synthesis approach. Most of previous works have focused on BDD size reduction during logic synthesis. In this work, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization. Our contributions are threefold: (1) we propose a gain-based clustering and partial collapsing algorithm to prepare the initial design for BDD synthesis for better delay; (2) we use a technique named linear expansion for BDD decomposition, which in turn enables a dynamic programming algorithm to efficiently search through the optimization space for the BDD of each node in the clustered circuit; (3) we consider special decomposition scenarios coupled with linear expansion for further improvement on quality of results. Experimental results show that we can achieve a 95% gain in terms of network depths, and a 20% gain in terms of routed delay, with a 22% area overhead on average compared to a previous state-of-art BDD-based FPGA synthesis tool, BDS-pga.
Starting Page	910
Ending Page	915
File Size	343282
Page Count	6
File Format	PDF
ISBN	9781595936271
ISSN	0738100X
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Delay Binary decision diagrams Field programmable gate arrays Optimization Clustering algorithms Logic Algorithm design and analysis Circuit synthesis Dynamic programming Heuristic algorithms linear expansion Algorithm Performance FPGA technology mapping binary decision diagrams
Content Type	Text
Resource Type	Article

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DDBDD: delay-driven BDD synthesis for FPGAs

DDBDD: Delay-Driven BDD Synthesis for FPGAs

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