NDLI: Global Critical Path: A Tool for System-Level Timing Analysis

Content Provider	IEEE Xplore Digital Library
Author	Venkataramani, G. Budiu, M. Chelcea, T. Goldstein, S.C.
Copyright Year	2007
Description	Author affiliation: Carnegie Mellon Univ., Pittsburgh (Venkataramani, G.)
Abstract	An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is defined at the RTL level, as the longest path in the combinational logic between clocked registers. In this paper, we present a system-level timing analysis technique to define the concept of a global critical path (GCP), for predicting system-level performance. We show how the GCP can be used as a theoretical and practical tool for understanding, summarizing and optimizing the behavior of highly concurrent self-timed circuits. We formally define the GCP and show how it can be constructed using a discrete event model and hardware profiling techniques. The GCP provides valuable insight into the control-path behavior of circuits and in finding system-level bottlenecks. We have incorporated the GCP construction and analysis framework into a high-level synthesis and simulation toolchain, thus enabling complete automation in modeling, analysis and optimization.
Starting Page	783
Ending Page	786
File Size	310704
Page Count	4
File Format	PDF
ISBN	9781595936271
ISSN	0738100X
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Timing Circuits Design optimization Logic Clocks Registers Performance analysis Hardware Automatic control Control systems Hardware profiling Design Measurement Performance Global critical path System modeling
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Global critical path: a tool for system-level timing analysis

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Minimum buffer insertions for clock period minimization

Abstraction of data path registers for multilevel verification of large circuits

Incremental timing optimization for automatic layout generation

Solvability of simultaneous control step and timing skew assignments in high level synthesis

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Register transfer level VHDL models without clocks

Register binding for clock period minimization

Global Critical Path: A Tool for System-Level Timing Analysis

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