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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wiggers, M.H. Bekooij, M.J.G. Smit, G.J.M. |
| Copyright Year | 2007 |
| Description | Author affiliation: Univ. of Twente, Enschede (Wiggers, M.H.) |
| Abstract | A key step in the design of cyclo-static real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure, which means that tasks wait for space in output buffers. Consequently buffer capacities affect the throughput. This requires the derivation of buffer capacities that both result in a satisfaction of the throughput constraint, and also satisfy the constraints on the maximum buffer capacities. Existing exact solutions suffer from the computational complexity that is associated with the required conversion from a cyclo-static dataflow graph to a single-rate dataflow graph. In this paper we present an algorithm, with polynomial computational complexity, that does not require this conversion and that obtains close to minimal buffer capacities. The algorithm is applied to an MP3 play-back application that is mapped on our multi-processor system. For this application, we see that a cyclo-static dataflow model can reduce the buffer capacities by 50% compared to a multi-rate dataflow model. |
| Starting Page | 658 |
| Ending Page | 663 |
| File Size | 594361 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781595936271 |
| ISSN | 0738100X |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-06-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Throughput Delay Permission Polynomials Real time systems Computational complexity System-on-a-chip Streaming media Containers Runtime Buffer Capacity Algorithms Design Performance System-on-Chip Dataflow |
| Content Type | Text |
| Resource Type | Article |
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