NDLI: Nanometer Device Scaling in Subthreshold Circuits

Please wait, while we are loading the content...

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

DAC Design Automation Conference 2012

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

Design Automation Conference

2009 46th ACM/IEEE Design Automation Conference

2008 45th ACM/IEEE Design Automation Conference

2007 44th ACM/IEEE Design Automation Conference

General Chair's Message

A. Richard Newton, 1951 - 2007

Executive Committee

Technical Program Committee

Tutorial Committee

Panel Committee

Exhibitor Liaison Committee

Strategy Committee

Student Design Contest Judges

Designing a New Automotive DNA

Perspective of the Future Semiconductor Industry: Challenges and Solutions

Design without Borders - A Tribute to the Legacy of A. Richard Newton

Marie R. Pistilli Women in EDA Achievement Award

Call for Papers

Table of contents

Trusted Hardware: Can It Be Trustworthy?

Trusted Design in FPGAs

Physical Unclonable Functions for Device Authentication and Secret Key Generation

Side-Channel Attack Pitfalls

Megatrends and EDA 2017

System-Level Design Flow Based on a Functional Reference for HW and SW

Model-driven Validation of SystemC Designs

Language Extensions to SystemC: Process Control Constructs

Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264

Design of Rotary Clock Based Circuits

Escape Routing For Dense Pin Clusters In Integrated Circuits

TROY: Track Router with Yield-driven Wire Planning

IPR: An Integrated Placement and Routing Algorithm

An Effective Guidance Strategy for Abstraction-Guided Simulation

Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation

Synthesizing SVA Local Variables for Formal Verification

Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization

Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift

Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation

Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage

Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits

Making Manufacturing Work For You

Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip

Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT

Layered Switching for Networks on Chip

Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands

The Case for Low-Power Photonic Networks on Chip

Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations

PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels

Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis

Simulating Improbable Events

SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits

On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise

Optimal Selection of Voltage Regulator Modules in a Power Delivery Network

Top-k Aggressors Sets in Delay Noise Analysis

A New Twisted Differential Line Structure in Global Bus Design

Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew

Formal Techniques for SystemC Verification; Position Paper

Design for Verification in System-level Models and RTL

Verification Methodologies in a TLM-to-RTL Design Flow

Memory Modeling in ESL-RTL Equivalence Checking

Early Power-Aware Design & Validation: Myth or Reality?

Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design

A System For Coarse Grained Memory Protection In Tiny Embedded Processors

Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors

A Memory-Conscious Code Parallelization Scheme

A Self-Tuning Configurable Cache

Comparative Analysis of Conventional and Statistical Design Techniques

Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction

Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources

Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting

Chip Multi-Processor Generator

The Case for the Precision Timed (PRET) Machine

Quantum-Like Effects in Network-on-Chip Buffers Behavior

CAD-based Security, Cryptography, and Digital Rights Management

Line-End Shortening is Not Always a Failure

You Can Get There From Here: Connectivity of Random Graphs on Grids

High Performance and Low Power Electronics on Flexible Substrate

Novel CNTFET-based Reconfigurable Logic Gate Design

Period Optimization for Hard Real-time Distributed Automotive Systems

Performance Analysis of FlexRay-based ECU Networks

Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application

Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture

Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications

Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors

GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches

Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits

Single-Event-Upset (SEU) Awareness in FPGA Routing

Enhancing FPGA Performance for Arithmetic Circuits

Fast Min-Cost Buffer Insertion under Process Variations

Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks

Concurrent Wire Spreading, Widening, and Filling

Modeling Litho-Constrained Design Layout

Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement

The Impact of NBTI on the Performance of Combinational and Sequential Circuits

NBTI-Aware Synthesis of Digital Circuits

"There Is More Than Moore In Automotive ...."

Modeling Safe Operating Area in Hardware Description Languages

Autonomous Automobiles: Developing Cars That Drive Themselves

Design-Silicon Timing Correlation A Data Mining Perspective

Silicon Speedpath Measurement and Feedback into EDA flows

Characterizing Process Variation in Nanometer CMOS

On-Chip Measurements Complementary to Design Flow for Integrity in SoCs

Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits

Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System

Synchronous Elastic Circuits with Early Evaluation and Token Counterflow

Optimization of Area in Digital FIR Filters using Gate-Level Metrics

Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency

Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops

Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical Preconditioning

Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch

TLM: Crossing Over From Buzz To Adoption

Electronics: The New Differential in the Automotive Industry

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization

Improving Voltage Assignment by Outlier Detection and Incremental Placement

Analog Placement Based on Novel Symmetry-Island Formulation

Modeling the Function Cache for Worst-Case Execution Time Analysis

An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration

Hardware Support for Secure Processing in Embedded Systems

RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks

Compact State Machines for High Performance Pattern Matching

Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations

Statistical Framework for Technology-Model-Product Co-Design and Convergence

Extraction of Statistical Timing Profiles Using Test Data

An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires

Scan Test Planning for Power Reduction

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design

New Test Data Decompressor for Low Power Applications

Automotive Software Integration

Virtual Platforms and Timing Analysis: Status, Challenges and Future Directions

Computer-aided Architecture Design & Optimized Implementation of Distributed Automotive EE Systems

Interconnects in the Third Dimension: Design Challenges for 3D ICs

Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects

Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations

CAD Implications of New Interconnect Technologies

Alembic: An Efficient Algorithm for CNF Preprocessing

EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure

On-The-Fly Resolve Trace Minimization

On Resolution Proofs for Combinational Equivalence

An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design

Computationally Efficient Power Integrity Simulation for System-on-Package Applications

Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design

Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors

Placement of 3D ICs with Thermal and Interlayer Via Considerations

Corezilla: Build and Tame the Multicore Beast?

Synthetic biology: from bacteria to stem cells

Engineering synthetic killer circuits in bacteria

Programming Living Cells to Function as Massively Parallel Computers

Synthesizing Stochasticity in Biochemical Systems

Instruction Splitting for Efficient Code Compression

An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model

Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs

Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution Time

A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip

SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects

A DFT Method for Time Expansion Model at Register Transfer Level

Test Generation in the Presence of Timing Exceptions and Constraints

Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design

Nanometer Device Scaling in Subthreshold Circuits

Efficient Modeling Techniques for Dynamic Voltage Drop Analysis

On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method

Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory

Shared Resource Access Attributes for High-Level Contention Models

A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices

Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling

Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution

Verification Coverage: When is Enough, Enough?

Thousand Core ChipsA Technology Perspective

The KILL Rule for Multicore

Implicitly Parallel Programming Models for Thousand-Core Microprocessors

Multi-Core Design Automation Challenges

Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures

Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs

Global Critical Path: A Tool for System-Level Timing Analysis

Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification

RISPP: Rotating Instruction Set Processing Platform

ASIP Instruction Encoding for Energy and Area Reduction

Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures

Program Mapping onto Network Processors by Recursive Bipartitioning and Refining

Design Methodology for Pipelined Heterogeneous Multiprocessor System

A General Framework for Spatial Correlation Modeling in VLSI Design

Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation

A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis

Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method

A Unified Approach to Canonical Form-based Boolean Matching

Gate Sizing For Cell Library-Based Designs

Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization

Techniques for Effective Distributed Physical Synthesis

SODA: Sensitivity Based Optimization of Disk Architecture

Dynamic Power Management with Hybrid Power Sources

System-on-Chip Power Management Considering Leakage Power Variations

Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation

A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages

Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation

Automatic Verification of External Interrupt Behaviors for Microprocessor Design

A Framework for the Validation of Processor Architecture Compliance

Functional Verification of SiCortex Multiprocessor System-on-a-Chip

DDBDD: Delay-Driven BDD Synthesis for FPGAs

FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs

How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs

Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits

Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop

Parameterized Macromodeling for Analog System-Level Design Exploration

Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies

Integrated Droplet Routing in the Synthesis of Microfluidic Biochips

OPC-Free and Minimally Irregular IC Design Style

Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits

Quantum Circuit Placement: Optimizing Qubit-to-qubit Interactions through Mapping Quantum Circuits into a Physical Experiment

Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si:H TFT Scan Driver

Clock Period Minimization with Minimum Delay Insertion

An Efficient Mechanism for Performance Optimization of Variable-Latency Designs

A Fully-Automated Desynchronization Flow for Synchronous Circuits

Self-Resetting Latches for Asynchronous Micro-Pipelines

IP Exchange: I'll Show You Mine if You Show Me Yours

2006 43rd ACM/IEEE Design Automation Conference

Proceedings. 42nd Design Automation Conference, 2005.

Proceedings. 41st Design Automation Conference, 2004.

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)

Proceedings 37th Design Automation Conference

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

Proceedings of the 34th Design Automation Conference

33rd Design Automation Conference Proceedings, 1996

32nd Design Automation Conference

31st Design Automation Conference

[1992] Proceedings 29th ACM/IEEE Design Automation Conference

28th ACM/IEEE Design Automation Conference

27th ACM/IEEE Design Automation Conference

26th ACM/IEEE Design Automation Conference

25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

24th ACM/IEEE Design Automation Conference

23rd ACM/IEEE Design Automation Conference

22nd ACM/IEEE Design Automation Conference

21st Design Automation Conference Proceedings

20th Design Automation Conference Proceedings

19th Design Automation Conference

18th Design Automation Conference

17th Design Automation Conference

16th Design Automation Conference

15th Design Automation Conference

30th ACM/IEEE Design Automation Conference

Nanometer Device Scaling in Subthreshold Circuits

Content Provider	IEEE Xplore Digital Library
Author	Hanson, S. Mingoo Seok Sylvester, D. Blaauw, D.
Copyright Year	2007
Description	Author affiliation: Univ. of Michigan, Ann Arbor (Hanson, S.; Mingoo Seok; Sylvester, D.; Blaauw, D.)
Abstract	Subthreshold circuit design is a strong candidate for use in future low power applications. It is not clear, however, that device scaling to 45 nm and beyond will be beneficial in subthreshold circuits. We investigate the implications of device scaling on subthreshold circuits and find that the slow scaling of gate oxide thickness leads to a 60 % reduction in $I_{on}/I_{off}$ between the 90 nm and 32 nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in $sub-V_{th}$ circuits.
Starting Page	700
Ending Page	705
File Size	602463
Page Count	6
File Format	PDF
ISBN	9781595936271
ISSN	0738100X
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Nanoscale devices Degradation Lead compounds Integrated circuit noise Delay effects Circuit noise Low voltage Timing MOSFETs Circuit synthesis ultra-low power Design Subthreshold circuits device scaling
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in