NDLI: Optimization of Area in Digital FIR Filters using Gate-Level Metrics

Content Provider	IEEE Xplore Digital Library
Author	Aksoy, L. Costa, E. Flores, P. Monteiro, J.
Copyright Year	2007
Description	Author affiliation: Istanbul Tech. Univ., Istanbul (Aksoy, L.)
Abstract	In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its effectiveness for digital FIR filters. Previous methods use the number of required additions or subtractions as a cost function. We make the observation that not all of these operations have the same design cost. In the proposed algorithm, a minimum area solution is obtained by considering area estimates for each operation. To this end, we introduce accurate hardware models for addition and subtraction operations in terms of gate-level metrics, under both signed and unsigned representations. Our algorithm not only computes the best design solution among those that have the same number of operations, but is also able to find better area solutions using a non-minimum number of operations. The results obtained by the proposed exact algorithm are compared with the results of the exact algorithm designed for the minimum number of operations on FIR filters and it is shown that the area of the design can be reduced by up to 18%.
Starting Page	420
Ending Page	423
File Size	265712
Page Count	4
File Format	PDF
ISBN	9781595936271
ISSN	0738100X
DOI	10.1109/DAC.2007.375200
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Finite impulse response filter Signal processing algorithms Algorithm design and analysis Cost function Hardware Digital signal processing Permission Arithmetic Logic Digital filters area optimization Multiple constant multiplication FIR
Content Type	Text
Resource Type	Article

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