NDLI: A Memory-Conscious Code Parallelization Scheme

Content Provider	IEEE Xplore Digital Library
Author	Liping Xue Ozturk, O. Kandemir, M.
Copyright Year	2007
Description	Author affiliation: Univ. of Delaware, Newark (Liping Xue; Ozturk, O.; Kandemir, M.)
Abstract	While there have been considerable work in the last couple of years for architecting embedded chip multiprocessors, programming and compiler support required for them took relatively less attention. Our goal in this paper is to show that conventional compiler-directed code parallelization used in high performance computing is not very suitable for embedded chip multiprocessors where minimizing memory space requirements is an important issue. We propose and evaluate a novel memory-conscious loop parallelization strategy with the objective of minimizing the data memory requirements of processors. The proposed approach, which is formulated as a branch-and-bound problem, accomplishes its objective by being careful in selecting the loops to parallelize in a given loop nest. Miscellaneous. Experimentation, Algorithms, Performance.
Starting Page	230
Ending Page	233
File Size	374257
Page Count	4
File Format	PDF
ISBN	9781595936271
ISSN	0738100X
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Optimization methods Parallel programming Program processors High performance computing Partitioning algorithms Engineering profession Memory Space Optimization Experimentation Algorithms Performance Code Parallelization Embedded CMP
Content Type	Text
Resource Type	Article

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