NDLI: An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model

Content Provider	IEEE Xplore Digital Library
Author	Jui-Chin Chu Wei-Chun Ku Shu-Hsuan Chou Tien-Fu Chen Jiun-ln Guo
Copyright Year	2007
Description	Author affiliation: Nat. Univ. of Chung Cheng, Chia-Yi (Jui-Chin Chu; Wei-Chun Ku; Shu-Hsuan Chou; Tien-Fu Chen; Jiun-ln Guo)
Abstract	Multithreading and multi-core processing have been shown to be powerful approaches for boosting a system performance by taking advantage of parallelism in applications. This paper presents a processor design by unifying RISC and multithreading DSP for the sophisticated multimedia applications with advanced standards such as H.264. The proposed design not only minimizes integration costs for embedded multithreading/multi-core design by independent coherent threads, but also reduces the memory bandwidth requirements by one-stop streaming buffer and a very fast data exchange mechanism. With the proposed techniques and appropriate programming model, we can achieve 78% reduction of memory bandwidth and 89% reduction of processing time in H.264 video encoding, compared to traditional single stream micro-processor.
Starting Page	652
Ending Page	657
File Size	1873649
Page Count	6
File Format	PDF
ISBN	9781595936271
ISSN	0738100X
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Multithreading Streaming media Bandwidth Power system modeling Multicore processing Boosting System performance Process design Reduced instruction set computing Digital signal processing H.264 Performance Design Experimentation VisoMT Multimedia Processor Programming model
Content Type	Text
Resource Type	Article

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