NDLI: Data retention voltage analysis of various low-power SRAM topologies

Content Provider	IEEE Xplore Digital Library
Author	Leochico, K. John, E.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas at San Antonio, San Antonio, TX, USA (Leochico, K.; John, E.)
Abstract	In this paper, we analyze and compare five different low-power SRAM cell topologies in terms of their data retention voltages (DRV). The circuit simulation and analysis was carried out using HSPICE with the 45 nm, 32 nm, and 22 nm low-power Predictive Technology Model (PTM) transistor models by setting the SRAM cells to an initial state and bringing the supply voltage down for different standby voltages. Based on these results, the standard 6T SRAM cell provides the lowest DRV out of all of the SRAM cells in this study at the 45 nm and 32 nm process nodes, but the 7T, 8T, and 10T SRAM cells provide better DRV performance at the 22 nm process node. These results give a first look at the effects that SRAM cell topology can have on DRV, and provide a starting point for future research into ultra low-power memory design.
Starting Page	913
Ending Page	916
File Size	607945
Page Count	4
File Format	PDF
ISBN	9781479941346
ISSN	15483746
e-ISBN	9781479941322
DOI	10.1109/MWSCAS.2014.6908564
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SRAM cells Transistors Topology Inverters Standards Mathematical model Data Retention Voltage (DRV)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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