NDLI: High-speed low-power decimation filter for wideband Delta-Sigma ADC

Content Provider	IEEE Xplore Digital Library
Author	Yi Xie Minglei Zhang Baoyue Wei Xiaohua Fan
Copyright Year	2014
Description	Author affiliation: Inst. of Microelectron., Beijing, China (Yi Xie; Minglei Zhang; Baoyue Wei; Xiaohua Fan)
Abstract	This paper discusses the design of high-speed low-power decimation filter for wideband Delta-Sigma ADC. It presents a low power decimation filter with programmable decimation ratios (32, 64 and 128) and sampling rates (624MHz, 312MHz and 208MHz) for LTE application. The decimation filter has five different operating modes and consists of three sinc filters, two halfband filters and a FIR filter. It uses power efficient polyphase decomposition filter with a wise clock distribution approach to minimize power consumption. The decimation filter is implemented in 130 nm CMOS process, which consumes 0.46 × 0.46 $mm^{2}$ cell area. Simulation results show that when Sigma-Delta modulator output sampling frequency is 624MHz, 312MHz and 208MHz, it consumes less than 4.6mW, 2.3mW and 1.5mW from 1.2V supply respectively. In addition, they all achieve a Signal-to-Noise Ratio of 69dB over the signal bandwidth.
Starting Page	591
Ending Page	594
File Size	591975
Page Count	4
File Format	PDF
ISBN	9781479941346
ISSN	15483746
e-ISBN	9781479941322
DOI	10.1109/MWSCAS.2014.6908484
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filters Clocks Power demand Modulation IIR filters Noise
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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