NDLI: A BIST scheme for high-speed Gain Cell eDRAM

Content Provider	IEEE Xplore Digital Library
Author	Bing Yan Yufeng Xie Rui Yuan Yinyin Lin
Copyright Year	2011
Description	Author affiliation: ASIC & System State Key Lab, Dept. of Microelectronics, Fudan University, 825 Zhangheng Rd, 201203, Shanghai, China (Bing Yan; Yufeng Xie; Rui Yuan; Yinyin Lin)
Abstract	A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set architecture (ISA) and hardware. A 4-stage pipeline for instruction execution makes at-speed test possible. Various kinds of tests, including single-address test, traversal test and refresh test, can be performed by executing different instruction combinations. An 8KB Gain Cell memory with the BIST is fabricated in 0.13µm CMOS technology. Silicon measurement on ATE shows that the BIST can perform at-speed test and measurement types mentioned above.
Starting Page	244
Ending Page	247
File Size	1137686
Page Count	4
File Format	PDF
ISBN	9781612841922
ISSN	2162755X
e-ISBN	9781612841939
e-ISBN	9781612841915
DOI	10.1109/ASICON.2011.6157167
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Silicon Clocks Built-in self-test Application specific integrated circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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