NDLI: Debugging methodology and timing analysis in CDC solution

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2011 9th IEEE International Conference on ASIC

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Technical session index

A behavior-based reconfigurable cache for the low-power embedded processor

A novel method for storage architecture of pipeline FFT processor

Design of resistant DPA three-valued counter based on SABL

Improvement of adiabatic domino circuits and its application in multi-valued circuits

Low power shift registers for megabits CMOS image sensors

High-parallel LDPC decoder with power gating design

A reconfigurable macro-pipelined DCT/IDCT accelerator

Scheduling to timing optimization for a novel high-level synthesis approach

High reliable digital signal processor for automotive application

A novel Differential fault analysis on AES-128

Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU

A hardware/software co-design approach for multiple-standard video bitstream parsing

ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs

Analysis of adaptive support-weight based stereo matching for hardware realization

A high performance sound source localization system based on macro-pipelined architecture

Research on design of a reconfigurable parallel structure targeted at LFSR

Using NOC technology to improve photoelectric encoder system for LAMOST spectroscopes

A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain

A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder

A two-way parallel CAVLC encoder for 4K×2K H.264/AVC

Multi-stage power gating based on controlling values of logic gates

A high speed reconfigurable face detection architecture

A coarse-grained reconfigurable computing unit

Battery state of charge estimation using adaptive subspace identification method

A new frequency compensation scheme for current-mode DC/DC converter

A high-performance PWM controller with adjustable current limit

Capacitor-free, fast transient response CMOS low-dropout regulator with multiple-loop control

A high efficiency current mode step-up/step-down DC-DC converter with smooth transition

A non-rectifier wireless power transmission system using on-chip inductor

An overview of charge pumping circuits for flash memory applications

Class-AB CMOS buffer with floating class-AB control

A new topology for fully differential amplifiers that enhances their tolerance to external disturbances

Double charge pump circuit with triple charge sharing clock scheme

CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction

ROIC with adaptive reset control for improving dynamic range of IR FPAs

A signal conditioner IC for inductive proximity sensors

A low-power low-noise amplifier for EEG/ECG signal recording applications

A TIA-based interface for MEMS capacitive gyroscope

A multi-level arbitration and topology free streaming network for chip multiprocessor

Design and verification of an application-specific PLD using VHDL and SystemVerilog

Evaluation of deflection routing on various NoC topologies

ASIC implementation of an OFDM baseband transceiver for HINOC

Design of four-transistor Pixel for high speed CMOS image

A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip

Design of a signal processing circuit for quartz crystal microbalance biosensors

A low-power 433MHz transmitter for battery-less Tire Pressure Monitoring System

A high performance and low cost video processing SoC for digital HDTV systems

A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications

A NoC-based multi-core architecture for IEEE 802.11i CCMP

A method of quadratic programming for mapping on NoC architecture

A channel estimator for LTE downlink mapped on a multi-core processor platform

Wideband spectrum sensing using the all-phase FFT

A robust frame synchronization scheme for Broadband Power-line Communication

FFT implementation with Multi-operand floating point units

General lattice wave digital filter with phase compensation scheme

A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems

System modeling and analysis of the IEEE 802.15.4 physical layer design

Towards the next generation of low-power test technologies

Word error control algorithm through multi-reading for NAND Flash memories

A new scheme for testability improvement of ECC incorporated memory

A BIST scheme for high-speed Gain Cell eDRAM

Variation-resilient voltage generation for SRAM weak cell testing

Single event upset immune latch circuit design using C-element

Challenges of electrostatic discharge (ESD) protection in emerging silicon nanowire technology

A software/hardware co-debug platform for multi-core systems

HV CMOS orientated variation-aware layout and robust solution

Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs

Addressing fault tolerance in 4-PAM signaling by using block codes for on/off-chip communication

A novel multi-finger layout strategy for GGnMOS ESD protection device

Current status and future prospect of Phase Change Memory

Memristor models and circuits for controlling Process-VDD-Temperature variations

The design of low leakage SRAM cell with high SNM

Novel RRAM programming technology for instant-on and high-security FPGAs

A study of dual-Vt configurations of an 8T SRAM cell in 45nm

Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)

A 55nm ultra high density two-port register file compiler with improved write replica technique

Word line boost and read SA PMOS compensation (SAPC) for ROM in 55nm CMOS

Design of a single-ended cell based 65nm 32×32b 4R2W register file

A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidth

Separate projection and extended Cauer method for circuit reduction

VLSI interconnect delay analysis method for ramp input signal

RRA-based multi-objective optimization to mitigate the worst cases of placement

Numerical characterization of multi-dielectric green's function for floating random walk based capacitance extraction

Power grid sizing via convex programming

Polarity optimization of XNOR/OR circuit area and power based on weighted sum method

Don't let the X-bugs bite: Conquer elusive X-propagation issues early! Get them before they get you!

Meshim: A high-level performance simulation platform for three-dimensional network-on-chip

Through-Silicon-Via assignment for 3D ICs

Incremental layout optimization for NoC designs based on MILP formulation

Standard cell design of a low-leakage flip-flop with gate-length biasing

Debugging methodology and timing analysis in CDC solution

Circuit simulation using matrix exponential method

A new event driven testbench synthesis engine for FPGA emulation

An improved packing tool based on a dual-output basic logic element

A test approach of combining partial scan with functional testing for high performance processors

Automatic layout generator for embedded FPGA cores

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture

FPGA interconnect timing library based on the statistical method

Robustness and performance analysis on high speed ASIC design with canonical statistical timing model

Optimization of mixed polarity Reed-Muller expressions based on Whole Annealing Genetic Algorithm

CPIPQ: A common platform for silicon IP qualification

Comprehensive electro-thermal(ET) analysis with considering ET coupling

Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm

Mobility overlap-removal based timing-constrained scheduling

An effecient level-shifter floorplanning method for Multi-voltage design

The manufacturing of Si base thin film solar cell modules

Challenges and strategies in advanced CMOS technology development

Research on electromechanical model of micro-accelerometer based on SOI technology

CMOS compatible MEMs process for post interconnect single chip integration application

Cascadable current-mode multifunction filter configuration using minimum number of CCTAs and grounded capacitors

A matrix approach to low-voltage low-power log-domain CMOS current-mode adjustable-bandwidth step-gain filter design

A sigma-delta modulator with a novel chopper correlated double sampled integrator

VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter application

A continuous time sigma-delta modulator using time-domain quantizer and feedback element

An analysis on a pseudo-differential dynamic comparator with load capacitance calibration

Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications

A time-domain flash ADC immune to voltage controlled delay line non-linearity

A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array

A 1.8V 100MS/s 10-bit pipelined folding A/D converter with 9.49 ENOB at Nyquist frequency

A sample-and-hold circuit for 10-bit 100MS/s pipelined ADC

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS

A dual 12bit 80MSPS 3.3V Current-Steering DAC for HINOC

A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application

A new current switch driver with improved dynamic performance used for 500MS/s, 12-bit Nyquist current-steering DAC

A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS

A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters

Energy efficient ADC design with low voltage operation

A low-power 4.224GS/s sampler in 0.13-µm CMOS for IR UWB receiver

CMOS low-power subthreshold reference voltage utilizing self-biased body effect

A precision 2.5V bandgap voltage reference with excellent initial accuracy of 0.25% for high resolution ADCs

A high-performance bandgap reference with advanced curvature-compensation

Novel flash ion sensitive field effect transistor for chemical sensor applications

A model for energy quantization of single-electron transistor below 10nm

An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power

Linear Dropout Regulator based power distribution design under worst loading

A unipolar-CMOS with recessed source/drain load

An analytical model for SOI triple RESURF devices

A study of second saturation effect of OPTVLD NMOS

Quantum mechanical effects on the threshold voltage of the evenly doped surrounding-gate MOSFETs

Effect of structural parameters on the performance and variations of nanosizes PNIN tunneling field effect transistor

Exploring 3D power distribution network physics

An efficient solver for statistical capacitance extraction considering random process variations

Performance evaluation modeling for reconfigurable processor

A high performance clock precharge SEU hardened flip-flop

Design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter

A study of frequency synthesizer for AT-DMB applications

A new figure of Merit of LC oscilators considering frequency tuning range

Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOS

Design of a low-power low-phase-noise multi-mode divider with 25%-duty-cycle outputs in 0.13µm CMOS

A noise rejective VCO with build-in active LC filter

A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13µm CMOS

0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations

Digitally-controlled cell-based oscillator with multi-phase differential outputs

Low phase noise injection-locked doubler-based quadrature CMOS VCO

A thermal model for the top layer of 3D integrated circuits considering through silicon vias

Novel high uniformity readout circuit allowing microbolometers to operate with low noise

Integration of information security chips based on System-in-Package

A new asynchronous delay-insensitive link based on a 1-of-4 LETS code

A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline

An ultra low power ASK demodulator for passive UHF RFID tag

Improvement and parallel implementation of canny edge detection algorithm based on GPU

A new full current mode sense amplifier with compensation circuit

An efficient 90nm technology-node GHz transceiver of on-chip global interconnect

Electrochemical biosensor based on modified graphene oxide for tuberculosis diagnosis

Digital quadrature IF modulator using single-bit DACs

Zero-crossing distortion analysis in one cycle controlled boost PFC for Low THD

A simulation study of vertical tunnel field effect transistors

Determination of the trap states distribution in Poly-Si films using the OEMS modulation

High efficiency and low power multi-rate LDPC decoder design for CMMB

Area efficient LDPC decoder design for parallel layered decoding

Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs

Automatic compilation flow for a coarse-grained reconfigurable processor

Origin of high on-state current for dopant-segregated schottky MOSFET

System level performance evaluation of three-dimensional integrated circuit

An energy efficiency task scheduling algorithm for streaming applications on multiprocessor SoC

Analysis and architecture design of aggregation in BM3D

A JTAG-based configuration circuit applied in SerDes chip

An automated design flow for image processing filter in embedded systems

A novel channel estimation algorithm in OFDM power line communication system

Low power design for SoC with power management unit

Improvement on branch scheduling for VLIW architecture

Research on reconfigurable multiplier unit based on $GF[(2^{8})]^{4}$ field of symmetric cryptography

A low-voltage differential injection locked divider with forward body bias

Effects of unintended dopants on I–V characteristics of the double-gate MOSFETs, a simulation study

A control scheme for a 65nm 32×32b 4-read 2-write register file

Reflection analysis of signal transmission in 32-bit CPU based SiP

Research on testing of 32-bit CPU based SiP

A security processor based on MIPS 4KE architecture

Design of a reconfigurable network interface processor

A hardware accelerator for speech recognition applications

AProgrammable IP Core for LDPC Decoder Based onASIP

Parallel structure of GF $(2^{14})$ and GF $(2^{16})$ multipliers based on composite finite fields

A new method to improve the unconditional stability of InGaP/GaAs heterojunction bipolar transistor

An accurate physics-based method for calculating DC inductance of on-chip square multi-layer inductors

Dual frequency based Real Time Location System using passive UHF RFID

A reconfigurable linear array processor architecture for data parallel and computation intensive applications

A permutation network for configurable and scalable FFT processors

Comparison of 2D MESH routing algorithm in NOC

Simulation of carrier transport in quantum cascade lasers

Design of a UHF RFID tag baseband with the hummingbird cryptographic engine

A study on channel polarization and polar coding

A novel linear power amplifier for 2.6GHz LTE applications

Design of a monolithic low-power micro-sensor signal processing system

TSV based 3D IC wire length calculation algorithm

A new low power symmetric folded cascode amplifier by recycling current in 65nm CMOS technology

Ultra low voltage, wide tuning range voltage controlled ring oscillator

A 2.5V supply low noise CMOS amplifier using noise reduction technique of Chopper stabilization

Efficient floating random walk algorithm for interconnect capacitance extraction considering multiple dielectrics

A dual mode high efficiency buck DC-DC converter

A novel transimpedance amplifier for 10 Gbit/s optical communication system

Single event upset mitigation for FDP2008

Electro-thermal model extraction of power GaN HEMT using I–V pulsed and DC measurements

Characterization and analysis of pattern dependent variation-aware interconnects for a 65nm technology

Integrated Gm-C based PI controller for MEMS gyroscope drive loop

A subthreshold MOSFET bandgap reference with ultra-low power supply voltage

A highly linear wideband variable gain CMOS balun-LNA

A 65nm 10MHz single-inductor dual-output switching buck converter with time-multiplexing control

Design and implementation of pipelined TMVP multiplier using block recombination

A novel low THD 4-quadrant analog multiplier using feedforward compensation for PFC

An inductorless CMOS LNA with single input and differential output

A new nonlinear parameterized model order reduction technique combining the interpolation method and Proper Orthogonal Decomposition

A 0.6 ppm/°C current-mode bandgap with second-order temperature compensation

A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS

A sixth-order Chebyshev low-pass filter for single-chip UHF RFID reader

A realizable reconstruction filter for sampled data systems

Optimization of ADM with both restrictions of resolution and power dissipation in low supply voltage

A timing-perspective study on the wire model in placement

Design for testability of FFT/IFFT IP core for UWB systems

A CMOS hysteresis undervoltage lockout with current source inverter structure

A high linearity MOS capacitor for low voltage applications

A low-kickback preamplifier with offset cancellation for pipelined folding A/D Converter

Auto-assign method for large scale flip-chip package design

A 60GHz power amplifier using 90-nm RF-CMOS technology

The design and verification of SEU-hardened configurable DFF

Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm

Improved algorithm for Pareto front computation for CMOS OpAmp based on multi-objective genetic optimization

Calibration method considering second-order error term of timing skew for a novel multi-channel ADC

Large-signal MOSFET modeling by means of knowledge based fuzzy logic system

Design and application of reusable SoC verification platform

New power rail ESD clamp design with current starving technology

Design and implementation of a low Power Java Coprocessor for dual-interface IC Bank Card

A method to build reconfigurable architectures by extracting common subgraphs

A novel high-accuracy clock stabilizer with 50% duty cycle

A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process

Compensator design for digital controlled switched-mode power supplies

A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS

A novel RSD correction for pipeline ADC

A digital sliding mode controller for switching power supply converters

A low-power Gm-R-C image rejection filter for complex low-IF receiver

A 4GS/s 3b two-way time-interleaved ADC in 0.13um CMOS

A low power 1.0 GHz VCO in 65nm-CMOS LP-process

A charge-pump circuit to restrain reference spurs in the PLL

A wide lock-range, low jitter phase-locked loop for multi-standard SerDes application

Ultralow-power analog front-end IC design for an implantable cardioverter defibrillator (ICD)

A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver

An area-efficient dual-channel RF receiver for GPS-L1/Galileo-E1/Compass-B1

A 0.8-3GHz 40dB dynamic range CMOS variable-gain amplifier

A low-noise WCDMA transmitter with 25%-duty-cycle LO generator in 65nm CMOS

Power amplifier driver for SDR transmitter with high gain tuning range and dynamic power control

A 0.18µm CMOS 2.5Gbps pre-amplifier with AGC

Aluminum Nitride reconfigurable RF-MEMS front-ends

A low noise and highly linear 2.4-GHz RF front-end circuit for wireless sensor networks

An auto-calibrating I/Q mismatch scheme for high image rejection GPS RF receiver

A dual-mode analog baseband utilizing digital-assisted calibration for WCDMA/GSM receivers

A 0.25dB gain step high linear programmable gain amplifier

Reconfigurable low pass filter with Automatic Frequency Tuning for WCDMA and GSM application

A wide tuning range low-pass Gm-C filter for multi-mode wireless receivers with automatic frequency calibration

RFIDsense: A reconfigurable RFID sensor tag platform conforming to IEEE 1451.7 standard

Directional coupler design in 3G/LTE Power Amplifier Module (invited paper)

SiGe HBT Power Amplifier design using 0.35 µm BiCMOS technology with through-silicon-via

A 0.8–2.5GHz wideband SiGe BiCMOS low noise amplifier with noise fiugre of 1.98–3.3dB

Design of a high-linearity RF front-end with IP2 calibration for SAW-less WCDMA receivers

Architecture and design automation for application-specific processors

High-Level Synthesis: On the path to ESL design

A study of high-level synthesis: Promises and challenges

On virtual prototyping of embedded system-on-chips

2009 IEEE 8th International Conference on ASIC

2007 7th International Conference on ASIC

2005 6th International Conference on ASIC

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

2nd International Conference on ASIC

Debugging methodology and timing analysis in CDC solution

Content Provider	IEEE Xplore Digital Library
Author	Matsuda, A. Jin Zhang
Copyright Year	2011
Description	Author affiliation: Kyushu Embedded Forum, Fukuoka 8140001, Japan (Matsuda, A.) \|\| Technical Marketing, Real Intent, Sunnyvale, CA 94043, USA (Jin Zhang)
Abstract	As the design complexity of system LSI increasing, the number of clock domains also increases for system LSI designs. Due to the sheer volume of crossing signals and the different ways of crossing implementation, verifying clock domain crossings (CDC) has become a very important yet challenging task. Specialized CDC verification solution needs to be deployed to perform analysis of the design to accurately detect CDC issues as well as efficiently debug the root causes of these problems. This paper describes a case study on CDC verification for FPGA designs using Meridian CDC, Real Intent's clock domain crossing verification solution.
Starting Page	365
Ending Page	368
File Size	840490
Page Count	4
File Format	PDF
ISBN	9781612841922
ISSN	2162755X
e-ISBN	9781612841939
e-ISBN	9781612841915
DOI	10.1109/ASICON.2011.6157197
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Monitoring Jitter
Content Type	Text
Resource Type	Article

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