NDLI: A built-in self-test scheme for 3D RAMs

Content Provider	IEEE Xplore Digital Library
Author	Yun-Chao Yu Che-Wei Chou Jin-Fu Li Chih-Yen Lo Ding-Ming Kwai Yung-Fa Chou Cheng-Wen Wu
Copyright Year	2012
Description	Author affiliation: Department of Electrical Engineering, National Central University, Taoyuan, Taiwan 320 (Yun-Chao Yu; Che-Wei Chou; Jin-Fu Li; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu)
Abstract	Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIST scheme, a clock-domain-crossing-aware test pattern generator is proposed to cope with the clock-domain-crossing issue. An inter-die synchronization mechanism is also proposed to synchronize the BIST circuits in different dies. Furthermore, the BIST circuit provides the high-programmability feature to support the selection of RAMs in a die for testing such that it can support thermal management during the test. We design the proposed BIST scheme in a 3D IC with processor and RAM dies. Experimental results show that the area cost of the BIST circuit is very small. The area overhead of the BIST circuit for four 8192×64-bit RAMs in a die is only 0.45% using TSMC 90nm 1P9M CMOS process technology.
Starting Page	1
Ending Page	9
File Size	324836
Page Count	9
File Format	PDF
ISBN	9781467315944
ISSN	10893539
e-ISBN	9781467315951
DOI	10.1109/TEST.2012.6401579
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Random access memory Synchronization Clocks Through-silicon vias March test 3D Random Acces Memory built-in self-test through-silicon-via
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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