NDLI: High efficiency and low power multi-rate LDPC decoder design for CMMB

Content Provider	IEEE Xplore Digital Library
Author	Jiang xiaobo li hongyuan
Copyright Year	2011
Description	Author affiliation: School of Electronic and Iinformation Engineering, South China University of Technology, Guangzhou, Guangdong 510641, China (Jiang xiaobo; li hongyuan)
Abstract	High efficiency and low power LDPC decoder for CMMB that supports two rates has been designed in the paper. Layered min-sum algorithm and memory compression technology are adopted to reduce the usage of memory; backup memory method is applied to solve memory read/write conflict existing in CMMB LDPC code at a low cost of memory resource; operational unit multiplexing which can process 1/2 bit rate and 3/4 bit rate simultaneously is used so that the resource consumption of operational unit is reduced. The LDPC decoder designed in this paper is synthesized in the SMC0.18um process. The synthesized result has indicated that the area of designed CMMB LDPC decoder is 7.6mm2 and its power consumption is 132.8mW.
Starting Page	673
Ending Page	678
File Size	1177825
Page Count	6
File Format	PDF
ISBN	9781612841922
ISSN	2162755X
e-ISBN	9781612841939
e-ISBN	9781612841915
DOI	10.1109/ASICON.2011.6157295
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parity check codes Decoding Indexes Quantization Field programmable gate arrays FPGA low density parity check (LDPC) China mobile multimedia broadcasting (CMMB) decoder
Content Type	Text
Resource Type	Article

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