NDLI: A charge-pump circuit to restrain reference spurs in the PLL

Content Provider	IEEE Xplore Digital Library
Author	Changhong Huan Xiushan Wu Dan Wang
Copyright Year	2011
Description	Author affiliation: College of Electrical & Information Engineering, Anhui University of Technology, Ma'anshan, China (Dan Wang) \|\| College of Electrical & Mechanical Engineering of China Jiliang University, Hangzhou, China (Changhong Huan; Xiushan Wu)
Abstract	In the charge pump phase locked loop (CPPLL), the non-ideal characteristics of charge pump are the main causes of the reference spurs. Therefore, reducing the variety of non-ideal characteristics is one of the challenges in the CP design. In this paper, an improved charge pump circuit, based on the TSMC's 0.18µmCMOS process, has been designed and completed. An operational amplifier and self-biasing cascode current mirror and supply-independent reference current source are used in the CP design to make charge and discharge current matched. The charge pump has characteristics of low power consumption, high speed, good linearity, and high current matching.
Starting Page	1010
Ending Page	1013
File Size	863643
Page Count	4
File Format	PDF
ISBN	9781612841922
ISSN	2162755X
e-ISBN	9781612841939
e-ISBN	9781612841915
DOI	10.1109/ASICON.2011.6157378
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitance Discharges Generators Frequency synthesizers Charge pumps CMOS integrated circuits Phase frequency detector reference spurs phase locked loop charge pump current matching
Content Type	Text
Resource Type	Article

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